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| 型號： | TSB41AB3 |
| 英文描述： | IC APEX 20KE FPGA 400K 672-FBGA |
| 中文描述： | 3個IEEE 1394a端口電纜收發(fā)器/仲裁器 |
| 文件頁數(shù)： | 44/50頁 |
| 文件大?。?/td> | 662K |
| 代理商： | TSB41AB3 |
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SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
44
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
interface reset and disable (continued)
The sequence of events for resetting the PHY-LLC interface when it is in the nondifferentiated mode of operation
(ISO terminal is high) is as follows:
1
a.
Normal operation. Interface is operating normally, with LPS asserted, SYSCLK active, status and
packet data reception and transmission via the CTL and D lines, and request activity via the LREQ line.
In the above diagram, the LPS signal is shown as a non-pulsed level signal. However, it is permissible
to use a pulsed signal for LPS in a direct connection between the PHY and LLC; a pulsed signal is
required when using an isolation barrier (whether of the TI bus holder type or Annex J type).
LPS deasserted. The LLC deasserts the LPS signal and, within 1
μ
s, terminates any request or interface
bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low.
Interface reset. After T
LPS_RESET
time, the PHY determines that LPS is inactive, terminates any
interface bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset
state.
Interface restored. After the minimum T
RESTORE
time, the LLC may again assert LPS active. When LPS
is asserted, the interface initializes as described below.
b.
c.
d.
If the LLC continues to keep the LPS signal deasserted, it requests that the interface be disabled. The PHY
disables the interface when it observes that LPS has been deasserted for T
LPS_DISABLE
. When the interface
is disabled, the PHY sets its CTL and D outputs as stated above for interface reset, but also stops SYSCLK
activity. The interface is also placed into the disabled condition upon a hardware reset of the PHY. The timing
for interface disable is shown in Figure 24 and Figure 25.
When the interface is disabled, the PHY enters a low-power state if none of its ports is active.
SYSCLK
ISO
(Low)
(a)
(c)
(b)
CTL0, CTL1
D0
–
D7
LREQ
LPS
(d)
TLPS_RESET
TLPS_DISABLE
TLPSL
TLPSH
Figure 24. Interface Disable, ISO Low
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB41BA3-EP | IC APEX 20KE FPGA 400K 672-FBGA |
| TSB41LV03PFP | IC APEX 20KE FPGA 600K 652-BGA |
| TSB41AB2I | IEEE 1394a-2000 TWO-PORT CABLE TRANSCEVER/ARBITER |
| TSB41LV03AI | IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSC692E | 672-pin FineLine BGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB41AB3-EP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394A-2000 THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSB41AB3IPFP | 功能描述:緩沖器和線路驅(qū)動器 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| TSB41AB3IPFP | 制造商:Texas Instruments 功能描述:IC TRX/ARBITER 1394A 3 PORT 80HTQFP |
| TSB41AB3IPFPEP | 功能描述:1394 接口集成電路 Mil Enh 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB41AB3IPFPG4 | 制造商:Texas Instruments 功能描述:THREE PORT CBL TRNSCVR/ARBITER 1TX 1RX 400MBPS 80HTQFP - Rail/Tube |
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