參數(shù)資料
型號(hào)： TSB41AB3
英文描述： IC APEX 20KE FPGA 400K 672-FBGA
中文描述： 3個(gè)IEEE 1394a端口電纜收發(fā)器/仲裁器
文件頁(yè)數(shù)： 38/50頁(yè)
文件大?。?/td> 662K
代理商： TSB41AB3
SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
38
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
receive (continued)
The sequence of events for a normal packet reception is as follows:
1
a.
Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL
lines. Normally, the interface is idle when receive is asserted. However, the receive operation may
interrupt a status transfer operation that is in progress so that the CTL lines may change from status
to receive without an intervening idle.
Data-on indication. The PHY may assert the data-on indication code on the D lines for one or more
cycles preceding the speed-code.
Speed code. The PHY indicates the speed of the received packet by asserting a speed code on the D
lines for one cycle immediately preceding packet data. The link decodes the speed code on the first
receive cycle for which the D lines are not the data-on code. If the speed code is invalid, or indicates
a speed higher that that which the link is capable of handling, the link should ignore the subsequent data.
Receive data. Following the data-on indication (if any) and the speed-code, the PHY asserts packet
data on the D lines with receive on the CTL lines for the remainder of the receive operation.
b.
c.
d.
e.
Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL
lines. The PHY asserts at least one cycle of idle following a receive operation.
00
00
10
XX
(a)
(b)
(c)
FF (Data-On)
D0
–
D7
CTL0, CTL1
SYSCLK
00
01
Figure 19. Null Packet Reception Timing
The sequence of events for a null packet reception is as follows:
1
a.
Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL
lines. Normally, the interface is idle when receive is asserted. However, the receive operation may
interrupt a status transfer operation that is in progress so that the CTL lines may change from status
to receive without an intervening idle.
b.
Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles.
c.
Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL
lines. The PHY asserts at least one cycle of idle following a receive operation.
Table 20. Receive Speed Codes
D0
–
D7
00XX XXXX
0100 XXXX
0101 0000
1YYY YYYY
DATA RATE
S100
S200
S400
data-on indication
NOTE: X = Output as 0 by PHY, ignored by LLC.
Y = Output as 1 by PHY, ignored by LLC.
相關(guān)PDF資料
PDF描述
TSB41BA3-EP IC APEX 20KE FPGA 400K 672-FBGA
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TSB41AB2I IEEE 1394a-2000 TWO-PORT CABLE TRANSCEVER/ARBITER
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