參數(shù)資料
型號: TSB41AB3IPFPEP
廠商: Texas Instruments
文件頁數(shù): 3/55頁
文件大?。?/td> 0K
描述: IC 3PRT CABLE TXRX/ARBIT 80HTQFP
標(biāo)準(zhǔn)包裝: 96
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 6/6
規(guī)程: IEEE 1394
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 80-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 80-HTQFP(12x12)
包裝: 托盤
產(chǎn)品目錄頁面: 882 (CN2011-ZH PDF)
其它名稱: 296-22528
V62/03612-01XE
TSB41AB3EP
IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER
SGLS122C JULY 2002 REVISED JUNE 2008
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VDD
Source power node
3
3.3
3.6
V
Supply voltage, VDD
Non-source power node
3
3.3
3.6
V
High-level input voltage, VIH
Case1 (bus holder): ISO = VDD, VDD(5V) = VDD
Case2 (5 V Tol): ISO = VDD, VDD(5V) = 5 V
LREQ, CTL0, CTL1, D0D7
2.6
V
High-level input voltage, VIH
C/LKON, PC0, PC1, PC2, ISO, PD
0.7
×VDD
V
RESET
0.6
×VDD
Low-level input voltage, VIL
Case1 (bus holder): ISO = VDD, VDD(5V) = VDD
Case2 (5 V Tol): ISO = VDD, VDD(5V) = 5 V
LREQ, CTL0, CTL1, D0D7
1.2
V
Low-level input voltage, VIL
C/LKON, PC0, PC1, PC2, ISO, PD
0.2
×VDD
V
RESET
0.3
×VDD
Output current, IO
TPBIAS outputs
5.6
1.3
mA
Differential input voltage, VID
Cable inputs, during data reception
118
260
mV
Differential input voltage, VID
Cable inputs, during arbitration
168
265
mV
Common-mode input voltage, VIC
TPB cable inputs, Source power node
0.4706
2.515
V
Common-mode input voltage, VIC
TPB cable inputs, Nonsource power node
0.4706
2.015
V
Power-up reset time, t(pu)
RESET input
2
ms
TPA, TPB cable inputs, S100 operation
±1.08
Receive input jitter
TPA, TPB cable inputs, S200 operation
±0.5
ns
Receive input jitter
TPA, TPB cable inputs, S400 operation
±0.315
ns
Between TPA and TPB cable inputs, S100 operation
±0.8
Receive input skew
Between TPA and TPB cable inputs, S200 operation
±0.55
ns
Receive input skew
Between TPA and TPB cable inputs, S400 operation
±0.5
ns
All typical values are at VDD = 3.3 V and TA = 25°C.
For a node that does not source power; see Section 4.2.2.2 in IEEE 1394a-2000.
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