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參數(shù)資料
| 型號： | TSB41AB3IPFPEP |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 37/55頁 |
| 文件大小： | 0K |
| 描述： | IC 3PRT CABLE TXRX/ARBIT 80HTQFP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 6/6 |
| 規(guī)程： | IEEE 1394 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 80-HTQFP（12x12） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 882 (CN2011-ZH PDF) |
| 其它名稱： | 296-22528 V62/03612-01XE |
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TSB41AB3EP
IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER
SGLS122C JULY 2002 REVISED JUNE 2008
42
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
transmit (continued)
00
(e)
(d)
(c)
(b)
(a)
01
00
11
D0–D7
CTL0, CTL1
SYSCLK
00
Link controls CTL and D
PHY High-Impedance CTL and D outputs
Figure 22. Cancelled/Null Packet Transmission
The sequence of events for a cancelled/null packet transmission is as follows:1
a.
Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control
of the interface to the link.
b.
Optional idle cycle. The link may assert at most one idle cycle preceding assertion of hold. This idle cycle
is optional; the link is not required to assert idle preceding hold.
c.
Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of idle. These
hold cycle(s) are optional; the link is not required to assert hold preceding idle.
d.
Null transmit termination. The null transmit operation is terminated by the link asserting two cycles of
idle on the CTL lines and then releasing the interface and returning control to the PHY. Note that the
link may assert idle for a total of three consecutive cycles if it asserts the optional first idle cycle but does
not assert hold. It is recommended that the link assert three cycles of idle to cancel a packet
transmission if no hold cycles are asserted. This ensures that either the link or PHY controls the
interface in all cycles.
e.
After regaining control of the interface, the PHY asserts at least one cycle of Idle before any subsequent
status transfer, receive operation, or transmit operation.
interface reset and disable
The LLC controls the state of the PHY-LLC interface using the LPS signal. The interface may be placed into a
reset state, a disabled state, or be made to initialize and then return to normal operation. When the interface
is not operational (whether reset, disabled, or in the process of initialization) the PHY cancels any outstanding
bus request or register read request, and ignores any requests made via the LREQ line. Additionally, any status
information generated by the PHY is not queued and does not cause a status transfer upon restoration of the
interface to normal operation.
The LPS signal may be either a level signal or a pulsed signal, depending upon whether the PHY-LLC interface
is a direct connection or is made across an isolation barrier. When an isolation barrier exists between the PHY
and LLC (whether of the TI bus-holder type or Annex J type) the LPS signal must be pulsed. In a direct
connection, the LPS signal may be either a pulsed or a level signal. Timing parameters for the LPS signal are
given in Table 21.
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| TSB41AB3PFPG4 | 功能描述:1394 接口集成電路 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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