參數(shù)資料
型號： TSB41AB3IPFPEP
廠商： Texas Instruments
文件頁數(shù)： 5/55頁
文件大小： 0K
描述： IC 3PRT CABLE TXRX/ARBIT 80HTQFP
標(biāo)準(zhǔn)包裝： 96
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 6/6
規(guī)程： IEEE 1394
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 80-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 80-HTQFP（12x12）
包裝： 托盤
產(chǎn)品目錄頁面： 882 (CN2011-ZH PDF)
其它名稱： 296-22528
V62/03612-01XE
TSB41AB3EP
IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER
SGLS122C JULY 2002 REVISED JUNE 2008
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of operating conditions (unless otherwise noted)
(continued)
device
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See Note 2
115
IDD
Supply current
See Note 3
97
mA
IDD
Supply current
See Note 4
75
mA
IDD(ULP) Supply current—ultralow power mode
VDD = 3.3 V,
TA = 25°C,
Ports disabled,
PD = 0 V,
LPS = 0 V
150
A
V(TH)
Power status threshold, CPS input
400-k
resistor
4.7
7.5
V
VOH
High-level output voltage, CTL0, CTL1,
VDD = 2.7 V,
IOH = 4 mA
2.2
V
VOH
High-level output voltage, CTL0, CTL1,
D0D7, CNA, C/LKON, SYSCLK outputs
VDD = 3 V to 3.6 V, IOH = 4 mA
2.8
V
VOL
Low-level output voltage, CTL0, CTL1,
D0D7, CNA, C/LKON, SYSCLK outputs
IOL = 4 mA
0.4
V
VOH(AJ)
High-level Annex J output voltage, CTL0,
CTL1, D0D7, C/LKON, SYSCLK outputs
Annex J: IOH = 9 mA,
ISO = 0 V,
VDD_5V = VDD
VDD ≥ 3 V
VDD0.4
V
VOL(AJ)
Low-level Annex J output voltage, CTL0,
CTL1, D0D7, C/LKON, SYSCLK outputs
Annex J: IOL = 9 mA,
ISO = 0 V,
VDD_5V = VDD
VDD ≥ 3 V
0.4
V
I(BH+)
Positive peak bus holder current, D0D7,
CTL0CTL1, LREQ
ISO = 3.6 V,
VDD = 3.6 V,
VI = 0 V to VDD,VDD_5V = VDD
0.05
1
mA
I(BH)
Negative peak bus holder current, D0D7,
CTL0CTL1, LREQ
ISO = 3.6 V,
VDD = 3.6 V,
VI = 0 V to VDD,VDD_5V = VDD
1.0
0.05
mA
II
Input current, LREQ, LPS, PD, TESTM,
SM, SE, PC0–PC2 inputs
ISO = 0 V, VDD = 3.6 V
1
A
IOZ
Off-state output current, CTL0, CTL1,
D0–D7, C/LKON I/O’s
VO = VDD or 0 V
±5
A
I(IRST)
Pullup current, RESET input, I device
VI = 1.5 V or 0 V
90
20
A
I(IRST)
Pullup current, RESET input, M device
VI = 1.5 V or 0 V
110
20
A
VIT+
Positive input threshold voltage, LREQ,
CTL0, CTL1, D0–D7 inputs
VDD_5V = VDD, ISO = 0 V
VDD ≥ 3 V
VDD/2+0.3
VDD/2+0.9
V
VIT+
Positive input threshold voltage, LPS inputs
VDD_5V = VDD, ISO = 0 V,
Vref = VDD × 0.4, VDD ≥ 3 V
Vref+1
V
VIT
Negative input threshold voltage, LREQ,
CTL0, CTL1, D0–D7 inputs
ISO = 0 V,
VDD_5V = VDD
VDD ≥ 3 V
VDD/20.9
VDD/20.3
V
VIT
Negative input threshold voltage, LPS
inputs
ISO = 0 V,
VDD_5V = VDD,
Vref = VDD × 0.4, VDD ≥ 3 V
Vref+0.2
V
VO
TPBIAS output voltage
At rated IO current
1.665
2.015
V
Measured at cable power side of resistor.
This parameter applicable only when ISO is low.
NOTES:
3. Transmit max packet (three ports transmitting max size isochronous packet—4096 bytes, sent on every isochronous interval, s400,
data value of 0xCCCCCCCCh), VDD = 3.3 V, TA = 25°C
4. Repeat typical packet (one port receiving DV packets on every isochronous interval, two ports repeating the packet, s100), VDD =
3.3 V, TA = 25°C
5. Idle (three ports transmitting cycle starts), VDD = 3.3 V, TA = 25°C
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