參數(shù)資料
型號(hào)： TSPC106AVGSU83CE
英文描述： MEMORY CONTROLLER
中文描述： 內(nèi)存控制器
文件頁(yè)數(shù)： 18/40頁(yè)
文件大小： 569K
代理商： TSPC106AVGSU83CE
18
TSPC106
2102B
–
HIREL
–
02/02
Interrupt, Clock and Power Management Signals
The TSPC106 coordinates interrupt, clocking, and power management signals across the memory bus, the PCI bus and
the 60x processor bus.
IEEE 1149.1 Interface Signals
To facilitate system testing, the TSPC106 provides a JTAG test access port that complies with the IEEE 1149.1 boundary-
scan specification.
Table 8.
Interrupt, Clock and Power Management Signals
Signal
Signal Name
Number of
Pins
I/O
Signal Description
CKO
DWE2
Test clock
1
O
CKO provides a means to monitor the internal PLL output or the bus
clock frequency. The CKO clock should be used for testing purposes
only. It is not intended as a reference clock signal.
HRST
Hard reset
1
I
Initiates a complete hard reset of the TSPC106. During assertion, all
bi-directional signals are released to a high-impedance state and all
output signals are either in a high impedance or inactive state.
NMI
Nonmaskable
interrupt
1
I
Indicates that an external device (typically an interrupt controller) has
detected a catastrophic error. In response, the TSPC106 asserts MCP
on the 60x processor bus.
QACK
Quiesce
acknowledge
1
O
Indicates that the TSPC106 is in a low-power state. All bus activity that
requires snooping has terminated and the 60x processor may enter a
low-power state.
QREQ
Quiesce request
1
I
Indicates that a 60x processor is requesting that all bus activity
involving snoop operations pause or terminate so that the 60x
processor may enter a low-power state.
SUSPEND
Suspend
1
I
Activates the suspend power-saving mode.
SYSCLK
System clock
1
I
SYSCLK sets the frequency of operation for the PCI bus and provides
a reference clock for the phase-locked loop (PLL) in the TSPC106.
SYSCLK is used to synchronize bus operations. Refer to section
“
Clocking
”
on page 19 for more information.
Table 9.
IEEE 1149.1 Interface Signals
Signal
Signal Name
Number of
Pins
I/O
Signal Description
TCK
JTAG test clock
1
I
Input signals to the test access port (TAP) are clocked in on the rising
edge of TCK. Changes to the TAP output signals occur on the falling
edge of TCK. The test logic allows TCK to be stopped.
TDO
JTAG test data
output
1
O
The contents of the selected internal instructions or data register are
shifted out onto this signal on the falling edge of TCK. TDO will remain
in a high-impedance state except when scanning of data is in progress.
TDI
JTAG test data
input
1
I
The value presented on this signal on the rising edge of TCK is clocked
into the selected JTAG test instruction or data register.
TMS
JTAG test mode
select
1
I
This signal is decoded by the internal JTAG TAP controller to
distinguish the primary operation of the test support circuitry.
TRST
JTAG test reset
1
I
This input causes asynchronous initialization of the internal JTAG TAP
controller.
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