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參數(shù)資料
| 型號： | TSPC106AVGSU83CE |
| 英文描述： | MEMORY CONTROLLER |
| 中文描述： | 內(nèi)存控制器 |
| 文件頁數(shù)： | 25/40頁 |
| 文件大?。?/td> | 569K |
| 代理商： | TSPC106AVGSU83CE |
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25
TSPC106
2102B
–
HIREL
–
02/02
Dynamic Characteristics
This section provides the AC electrical characteristics for the TSPC106. After fabrica-
tion, parts are sorted by maximum 60x processor bus frequency as shown in Table 16
and tested for conformance to the AC specifications for that frequency. These specifica-
tions are for operation between 16.67 and 33.33 MHz PCI bus (SYSCLK) frequencies.
The 60x processor bus frequency is determined by the PCI bus (SYSCLK) frequency
and the settings of the PLL[0:3] signals. All timings are specified relative to the rising
edge of SYSCLK.
Clock AC Specifications
Table 16 provides the clock AC timing specifications as defined in Figure 7.
Notes:
1. The SYSCLK frequency and PLL[0:3] settings must be chosen so that the resulting SYSCLK (bus) frequency, CPU (core)
frequency and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to
the PLL[0:3] signal description in
“
System Design Information
”
on page 33 for valid PLL[0:3] settings.
2. Rise and fall times for the SYSCLK input are measured from 0.4V to 2.4V.
3. Timing is guaranteed by design and characterization and is not tested.
4. The total input jitter (short-term and long-term combined) must be under ±200 ps.
5. PLL-relock time is the maximum time required for PLL lock after a stable V
DD
, AV
DD
, and SYSCLK are reached during the
power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently reenabled dur-
ing the sleep and suspend power-saving modes. Also note that HRST must be held asserted for a minimum of 255 bus
clocks after the PLL-relock time (100 ms) during the power-on reset sequence.
Figure 7.
SYSCLK Input Timing Diagram
Note:
VM = Midpoint Voltage (1.4V)
Table 16.
Clock AC Timing Specifications (V
DD
= 3.3V ± 5% dc, GND = 0V dc, -55
°
C
≤
T
C
≤
125
°
C)
Ref
Characteristic
SYSCLK/Core 33/66 MHz
SYSCLK/Core 33/83.3 MHz
Unit
Min
Max
Min
Max
60x processor bus (core) frequency
(1)
16.67
66
16.67
83.3
MHz
VCO frequency
(1)
150
400
150
400
MHz
SYSCLK frequency
(1)
16.67
33.33
16.67
33.33
MHz
1
SYSCLK cycle time
30.0
60.0
30.0
60.0
ns
2, 3
SYSCLK rise and fall time
(2)
2.0
2.0
ns
4
SYSCLK duty cycle measured at 1.4V
(3)
40
60
40
60
%
SYSCLK jitter
(4)
±200
±200
ps
106 internal PLL relock time
(3, 5)
100
100
μs
SYSCLK
VM
VM
VM
CVIL
CVIH
1
2
3
4
4
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