參數(shù)資料
型號(hào)： TSPC106AVGU83CE
英文描述： MEMORY CONTROLLER
中文描述： 內(nèi)存控制器
文件頁(yè)數(shù)： 33/40頁(yè)
文件大?。?/td> 569K
代理商： TSPC106AVGU83CE
33
TSPC106
2102B
–
HIREL
–
02/02
PCI Interface
The TSPC106
’
s PCI interface is compliant with the PCI Local Bus Specification, Revi-
sion 2.1, and follows the guidelines in the PCI System Design Guide, Revision 1.0 for
host bridge architecture. The PCI interface connects the processor and memory buses
to the PCI bus, to which I/O components are connected. The PCI bus uses a 32-bit mul-
tiplexed address/data plus various control and error signals.
The PCI interface of the TSPC106 functions as both a master and target device. As a
master, the TSPC106 supports read and write operations to the PCI memory space, the
PCI I/O space, and the PCI configuration space. The TSPC106 also supports PCI spe-
cial-cycle and interrupt-acknowledge commands. As a target, the TSPC106 supports
read and write operations to system memory. Mode selectable big-endian to little-endian
conversion is supplied at the PCI interface.
Internal buffers are provided for I/O operation between the PCI bus and the 60x proces-
sor or memory. Processor read and write operations each have a 32-byte buffer and
memory operation has one 32-byte read buffer and two 32-byte write buffers.
System Design
Information
This section provides electrical and thermal design recommendations for successful
application of the TSPC106.
PLL Configuration
The TSPC106 requires a single system clock input, SYSCLK. The SYSCLK frequency
dictates the frequency of operation for the PCI bus. An internal PLL on the TSPC106
generates a master clock that is used for all of the internal (core) logic. The master clock
provides the core frequency reference and is phase-locked to the SYSCLK input. The
60x processor, L2 cache and memory interfaces operate at the core frequency. In the
5:2 clock mode (Rev. 4.0 only), the TSPC106 needs to sample the 60x bus clock (on the
LBCLAIM configuration input) to resolve clock phasing with the PCI bus clock
(SYSCLK).
The PLL is configured by the PLL[0:3] signals. For a given SYSCLK (PCI bus) fre-
quency, the clock mode configuration signals (PLL[0:3]) set the core frequency (and the
frequency of the VCO controlling the PLL lock). The supported core and VCO frequen-
cies and the corresponding PLL[0:3] settings are provided in Table 19.
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