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  1. 參數(shù)資料
    型號(hào): TSPC106AVGU83CE
    英文描述: MEMORY CONTROLLER
    中文描述: 內(nèi)存控制器
    文件頁數(shù): 8/40頁
    文件大小: 569K
    代理商: TSPC106AVGU83CE
    8
    TSPC106
    2102B
    HIREL
    02/02
    Notes:
    1. Some signals have dual functions and are shown more than once in this table.
    2. All PCI signals are in little-endian bit order.
    3. This test signal is for factory use only. It must be pulled up to V
    DD
    for normal device operation.
    Signal Description
    The signals on the TSPC106 are grouped as follows:
    60x processor interface signals
    L2 cache/multiple processor interface signals
    Memory interface signals
    PCI interface signals
    Interrupt, clock and power management signals
    IEEE 1149.1 interface signals
    Configuration signals
    Note:
    A bar over a signal name indicates that the signal is active low, for example, address retry
    (ARTRY) and transfer start (TS). Active-low signals are referred to as asserted (active)
    when they are low and negated when they are high. Signals that are not active low such
    as tag valid (TV) and nonmaskable interrupt (NMI) are referred to as asserted when they
    are high and negated when they are low.
    Note:
    For multiple-function signals, outlined signal names refer to the alternate function(s) of
    the signal being described. For example, the L2 controller signal, (tag output enable
    TOE), has the alternate function data bus grant 1 (DBG1) when the TSPC106 is config-
    ured for a second 60x processor.
    PLL[0:3]
    U11, T11, U12, T12
    High
    Input
    TCK
    F13
    Clock
    Input
    TDI
    B13
    High
    Input
    TDO
    E12
    High
    Output
    TMS
    D14
    High
    Input
    TRST
    H13
    Low
    Input
    Power and Ground Signals
    AV
    DD
    LSSD_MODE
    (3)
    K9
    High
    Clock
    G11
    Low
    Input
    V
    DD
    E10, E6, F11, F5, F7, G10, G12, G6, H5, H7, K10, K7, L12, M11,
    M5, M7, N10, N12, N6, P11, P5, P7, R10, R6, J8, L8
    High
    Power
    V
    SS
    E11, E7, F10, F12, F6, G5, G7, H12, H6, J7, L7, M10, M12, M6,
    N11, N5, N7, P10, P12, P6, R11, R7, K8, J9, L9
    Low
    Ground
    NC
    H8, H9, M8, M9
    Table 1.
    TSPC106 Pinout in 303-ball CBGA Package (Continued)
    Signal Name
    Pin Number
    Active
    I/O
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