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參數(shù)資料
| 型號： | TSXPC603RVGB/Q14LC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 36/83頁 |
| 文件大?。?/td> | 8336K |
| 代理商： | TSXPC603RVGB/Q14LC |
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33
8021G–AVR–03/11
ATmega329P/3290P
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the
MCU is kept in Reset during such changes in the clock frequency.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to ”System Clock Prescaler” on page
33 for details.
8.8
Clock Output Buffer
When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This mode is
suitable when the chip clock is used to drive other circuits on the system. The clock will be out-
put also during reset and the normal operation of I/O pin will be overridden when the fuse is
programmed. Any clock source, including internal RC Oscillator, can be selected when CLKO
serves as clock output. If the System Clock Prescaler is used, it is the divided system clock that
is output when the CKOUT Fuse is programmed.
8.9
Timer/Counter Oscillator
ATmega329P/3290P uses the same crystal oscillator for Low-frequency Oscillator and
Timer/Counter Oscillator. See ”Low-frequency Crystal Oscillator” on page 30 for details on the
oscillator and crystal requirements.
ATmega329P/3290P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1
and XTAL2. When using the Timer/Counter Oscillator, the system clock needs to be four times
the oscillator frequency. Due to this and the pin sharing, the Timer/Counter Oscillator can only
be used when the Calibrated Internal RC Oscillator is selected as system clock source.
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is
written to logic one. See ”Asynchronous Operation of Timer/Counter2” on page 152 for further
description on selecting external clock as input instead of a 32.768kHz watch crystal.
8.10
System Clock Prescaler
The ATmega329P/3290P system clock can be divided by setting the Clock Prescale Register –
CLKPR. This feature can be used to decrease power consumption when the requirement for
processing power is low. This can be used with all clock source options, and it will affect the
clock frequency of the CPU and all synchronous peripherals. clk
I/O, clkADC, clkCPU, and clkFLASH
are divided by a factor as shown in Table 8-13 on page 36.
Table 8-12.
Start-up Times for the External Clock Selection
SUT1..0
Start-up Time from Power-
down and Power-save
Additional Delay from
Reset (V
CC = 5.0V)
Recommended Usage
00
6 CK
14CK
BOD enabled
01
6 CK
14CK + 4.1ms
Fast rising power
10
6 CK
14CK + 65ms
Slowly rising power
11
Reserved
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