參數(shù)資料
型號(hào)： TSXPC603RVGB/Q14LC
廠商： ATMEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 300 MHz, RISC PROCESSOR, CBGA255
封裝： 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255
文件頁(yè)數(shù)： 50/83頁(yè)
文件大?。?/td> 8336K
代理商： TSXPC603RVGB/Q14LC
49
32117D–AVR-01/12
AT32UC3C
6.2
Startup Considerations
This chapter summarizes the boot sequence of the AT32UC3C. The behavior after power-up is
controlled by the Power Manager. For specific details, refer to the Power Manager chapter.
6.2.1
Starting of clocks
At power-up, the BOD33 and the BOD18 are enabled. The device will be held in a reset state by
the power-up circuitry, until the VDDIN_33 (resp. VDDCORE) has reached the reset threshold of
the BOD33 (resp BOD18). Refer to the Electrical Characteristics for the BOD thresholds. Once
the power has stabilized, the device will use the System RC Oscillator (RCSYS, 115KHz typical
frequency) as clock source. The BOD18 and BOD33 are kept enabled or are disabled according
to the fuse settings (See the Fuse Setting section in the Flash Controller chapter).
On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have
a divided frequency, all parts of the system receive a clock with the same frequency as the inter-
nal RC Oscillator.
6.2.2
Fetching of initial instructions
After reset has been released, the AVR32UC CPU starts fetching instructions from the reset
address, which is 0x8000_0000. This address points to the first address in the internal Flash.
The internal Flash uses VDDIO voltage during read and write operations. It is recommended to
use the BOD33 to monitor this voltage and make sure the VDDIO is above the minimum level
(3.0V).
The code read from the internal Flash is free to configure the system to use for example the
PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the
clocks to unused peripherals.
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