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參數(shù)資料
| 型號： | TVP3020-175 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE(視頻接口調(diào)色器) |
| 中文描述： | 視頻接口盒（視頻接口調(diào)色器） |
| 文件頁數(shù)： | 13/98頁 |
| 文件大?。?/td> | 582K |
| 代理商： | TVP3020-175 |
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1–7
1.5
Terminal Functions (Continued)
PIN
I/O
DESCRIPTION
NAME
NO.
95
SFLAG
I
(TTL
compatible)
Split shift register transfer flag. The Viewpoint VIP detects a
low-to-high transition on this terminal during a blank sequence and
immediately generates an SCLK pulse. This early SCLK pulse
replaces the first SCLK pulse in the normal sequence.
System blank input. SYSBL is active (low).
SYSBL
91
I
(TTL
compatible)
SYSHS,
SYSVS
89, 90
I
(TTL
compatible)
System horizontal and vertical sync inputs. These signals are used to
generate the sync level on the green current output. They are active
(low) inputs, but the HSYNCOUT and VSYNCOUT outputs can be
programmed through general control register.
Video clock output. VCLK is the user-programmable output for
synchronization to graphics processor.
VCLK
111
O
(TTL
compatible)
VGABL
94
I
(TTL
capability)
VGA blank input. VGABL is active (low).
VGAHS,
VGAVS
92, 93
I
(TTL
capability)
VGA horizontal and vertical sync inputs. These signals are used to
generate the sync level on the green current output. They can be either
polarity, and the VIP passes the polarities to HSYNCOUT and
VSYNCOUT without change.
VGA0–VGA7
78–85
I
(TTL
capability)
VGA pass-through bus. These buses can be selected as the pixel bus
for VGA mode, but it does not allow for any multiplexing.
VSYNCOUT
62
O
(TTL
capability)
Vertical sync output after pipeline delay. For system mode, the output
can be programmed but for the VGA mode, the output carries the
same polarity as the input.
WR
37
I
(TTL
capability)
I
(TTL
capability)
Write strobe input. A logic 0 on this terminal initiates a write to the
register map. As with RD, write transfers are asynchronous and
initiated on the low-going edge of WR, (see Figure 3–1).
DAC resolution selection. This terminal is used to select the data bus
width (8 or 6 bits) for the DAC and is essentially provided in order to
maintain compatibility with the IMSG176. When this terminal is a
logical 1, 8-bit bus transfers are used with D7 the MSB and D0 the
LSB. For 6-bit bus operation, while the color palette still has the 8-bit
information D5 shifts to the bit 7 position with D0 shifted to the bit 2
position and the two LSBs are filled with zeros at the output multiplexer
to DAC. The palette holding register zeroes the two MSBs when it is
read in the 6-bit mode.
8/6
88
NOTE: All unused inputs should be tied to a logic level and not be allowed to float.
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3020-175MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-200MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3020-200PCE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3020-220MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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