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參數(shù)資料
| 型號： | TVP3020-175 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE(視頻接口調(diào)色器) |
| 中文描述： | 視頻接口盒（視頻接口調(diào)色器） |
| 文件頁數(shù)： | 67/98頁 |
| 文件大?。?/td> | 582K |
| 代理商： | TVP3020-175 |
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3–5
3.6 Switching Characteristics
PARAMETER
TVP3020-135
TYP
UNIT
MIN
MAX
SCLK frequency (CLOAD
≤
15 pF) (see Note 10)
SCLK frequency (CLOAD
≤
60 pF) (see Note 10)
RCLK/VCLK frequency (see Note 10)
Enable time, RD low to D(0 – 7) valid
Disable time, RD high to D(0 – 7) disabled
Valid time, D(0 – 7) valid after RD high
Propagation delay, SFLAG
↑
to SCLK high (see Note 10 and 11)
Delay time, RD low to D(0 – 7) starting to turn on
Delay time, selected input clock high/low to DOTCLK (internal signal)
high/low
Delay time, SCLK high/low to RCLK high/low (see Note 12)
Delay time, VCLK high/low to RCLK high/low (see Note 12)
Delay time, RCLK high/low from DOTCLK high/low (internal signal)
Delay time, LCLK from RCLK
Delay time, DOTCLK high to IOR/IOG/IOB active (analog output
delay time) (seeNote13)
Analog output settling time(seeNote 14)
Delay time, DOTCLK high to HSYNCOUT and VSYNCOUT valid
Analog output rise time (see Note 15)
Analog output skew
NOTES: 10. SCLK can drive an output capacitive load up to 60 pF. The worst-case transition time between the 10% and
90% levels is less than 4 ns (typical 3 ns). RCLK and VCLK can drive output capacitive loads up to 15 pF,
with worst case transition times between 10% and 90% levels less than 4 ns (typical 3 ns).
11. This parameter applies when the split shift register transfer (SSRT) function is enabled. See Section 2.15
for details.
12. The SCLK and VCLK delay time to RCLK depends on the load that the signals drive. This parameter is
measured with an RCLK to VCLK ratio of 1:1, and VCLK = RCLK load of 15 pF and SCLK load of 60 pF.
13. Measured from the 90% point of the rising edge of DOTCLK to 50% of the full-scale transition.
14. Measured from the 50% point of the full-scale transition to the point at which the output has settled, within
±
1 LSB (settling time does not include clock and data feedthrough).
15. Measured between 10% and 90% of the full-scale transition.
85
85
85
40
17
MHz
MHz
MHz
ns
ns
ns
ns
ns
ten1
tdis1
tv1
tPLH1
td1
5
0
5
20
td2
7
ns
td3
td4
td5
td6
1
1
2
3
7
5
6
ns
ns
ns
ns
tRCLK-7
td7
4
ns
td8
td9
tr
6
9
2
ns
ns
ns
ns
0
2
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| TVP3020-135 | Video Interface PALETTE(視頻接口調(diào)色器) |
| TVP3025-135 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| TVP3025-175 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| TVP3030-175 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| TVP3030-220 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3020-175MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-200MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3020-200PCE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3020-220MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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