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參數(shù)資料
| 型號： | TVP3020-175 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE(視頻接口調(diào)色器) |
| 中文描述： | 視頻接口盒（視頻接口調(diào)色器） |
| 文件頁數(shù)： | 21/98頁 |
| 文件大?。?/td> | 582K |
| 代理商： | TVP3020-175 |
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2–7
Table 2–5.
Output-Clock-Selection Register Format (Continued)
OUTPUT-CLOCK-SELECTION REGISTER BITS (see Note 4)
6
5
4
3
2
FUNCTION (see Notes 5, 6, and 7)
1
0
0
x
x
x
1
1
0
RCLK/64, SCLK output held at logic 0
0
x
x
x
1
1
1
RCLK, SCLK outputs held at logic 0
x
1
1
1
1
1
1
Clock counter reset (5)
These lines indicate the RESET conditions as required for VGA pass-through.
NOTES:
4 Register bit 6 enables (logic 1) and disables (default – logic 0) the SCLK output buffer. Register bit 7
is a don’t-care bit.
5 When the clocks are selected from one mode to the other, a minimum of 30 ns is needed before the
new clocks are stabilized and running.
6 When the output-clock-selection register is written with 3F (hex), the clock counter is reset,
RCLK = SCLK = logic 0, and VCLK = logic 1.
7 SCLK is the same as RCLK except that it is disabled during blank. When the RCLK divide ratio is
chosen, this sets the SCLK ratio as well.
2.3.2
The Viewpoint VIP has two pixel-data latching modes, allowing for flexibility in the frame-buffer interface
timing. For the pixel port (P0–P63), data is always latched on the rising edge of LCLK. If auxiliary-control
register (ACR) bit 3 is set to logic 1 (default), the internal circuitry is configured for self-clocked mode. In this
mode, the RCLK or SCLK output of the palette must be used as the timing reference to present data to the
pixel port (P0–P63). In self-clocked mode, RCLK can be directly tied back to LCLK or LCLK can be a
delayed version of RCLK within the timing requirements of the TVP3020. The self-clocked mode of
frame-buffer latching is similar to the operation of the TLC3407X video interface palette devices.
Frame-Buffer Clocking: Self or Externally Clocked
The internal Viewpoint blank signal is generated from either VGABL or SYSBL, depending on whether the
VGA port is enabled (multiplex-control register 2 (MCR2) bit 7 = logic 1) or disabled (MCR2 bit 7 = logic 0).
The rising edge of CLK0 is used to latch VGABL when the VGA port is enabled. The falling edge of VCLK
is used to sample and latch the SYSBL input when the VGA port is disabled. When the internal blank
becomes active, SCLK is disabled as soon as possible. For example, if SCLK is high when the sampled
SYSBL goes low, SCLK is allowed to complete the clock cycle and return to the low state. SCLK then is held
low until the sampled SYSBL signal goes back high. At this time, SCLK is enabled to clock the first pixel data
valid from VRAM. The Viewpoint video blanking circuitry is designed with sufficient pipeline delay to allow
the internal sampled SYSBL and VGABL signals to align with the pipelined RGB data to the video DACs.
The logic described above works in situations where the SCLK period is shorter than, equal to, or longer
than the VCLK period.
When in the self-clocked mode, the SCLK control timing is designed to interface directly with the external
VRAM. The shift register in the system VRAM is supposed to be updated during the blank active period.
When the SYSBL input is sampled high by the falling edge of VCLK, the VRAM shift clock (SCLK) is restarted
to clock the VRAM and enable the first group of pixel data to appear on the pixel bus as well as at the
Viewpoint pixel input port. The second SCLK causes the VRAM shift register to shift out the second group
of data. At the same time, LCLK latches the first group of pixel data into the Viewpoint palette (refer to
Figure 2–2 for a detailed timing diagram).
The RCLK/SCLK phase relationship is designed such that timing specifications are satisfied for the case
where SCLK is driving a typical 2-MB VRAM load and RCLK is connected to LCLK. If an external buffer is
required on SCLK so that it can drive a larger load, a similar buffer can be placed on RCLK to match the
signal delay before connecting to LCLK. However, the delay from LCLK to RCLK cannot exceed one RCLK
period –5 ns. Please refer to the timing parameter specifications for more details.
When the VRAM split-shift-register operation is performed (see Figure 2–3), the SCLK timing is adjusted
to work with the SFLAG input. Basically, the split-shift-register operation inserts an SCLK during the blank
period. This causes the first group of pixel data to appear at the pixel port during blank and allows the first
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相關(guān)代理商/技術(shù)參數(shù) |
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| TVP3020-175MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-200MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3020-200PCE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3020-220MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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