2–30
Color-key switching is performed according to the following equation:
COLOR–KEY = [(OL + CKC0)
×
(R + CKC1)
×
(G + CKC2)
×
(B + CKC3)]
⊕
CKC4
color-key OL/VGA low
≤
overlay or VGA (Note 24)
≤
color-key OL/VGA high
R = 1
if
color-key red low
≤
direct color (RED)
G = 1
if
color-key green low
≤
direct color (GREEN)
B = 1
if
color-key blue low
≤
direct color (BLUE)
where: OL = 1
if
≤
color-key red high
≤
color-key green high
≤
color-key blue high
then
if
if
COLOR–KEY = 1, overlay or VGA is displayed.
COLOR–KEY = 0, direct-color is displayed.
NOTES: 24. When the VGA port is activated (MCR2 bit 7 = 1), the OL/VGA register (low,high) color comparison is
performed on VGA data and the VGA port is color-key switched. If the VGA port is not activated (MCR2
bit 7 = 0) the comparison is performed on overlay data and overlay is color-key switched.
25. Color-key switching is supported for all direct-color multiplexing modes that have overlay capability when
doing overlay switching. When doing VGA switching, all direct-color modes are supported as long as the
multiplex ratio is 1:1. The direct-color multiplex mode is set in multiplex-control registers 1 and 2.
26. CKC0–CKC3 can be used to individually enable or disable certain colors in the comparison for maximum
flexibility. If color-key switching is not desired, CKC0–CKC3 should be set to logic 0. CKC4 is then used
to set the default for either direct color or palette graphics. The default condition at RESET is CKC0 = CKC1
= CKC2 = CKC3 = logic 0 and CKC4 = logic 1. This causes the function to default to palette graphics as
required for VGA pass-through node.
27. The color-key comparison for the overlay and VGA data is performed after the read mask and palette page
registers so that an 8-bit comparison can be performed. This also gives the maximum flexibility to the user
in performing the color comparisons. If the overlay defined for a given mode is less than 8 bits per pixel,
the data is shifted to the LSB locations and the palette-page register fills the remaining MSB positions.
28. For those direct-color modes that have less than 8 bits per pixel of red, green, and blue direct-color data,
the data is internally shifted to the MSB positions for each color and the remaining LSB bits are filled with
logic 0s before the 8-bit comparisons are performed.
29. The windowing and color-key functions are integrated such that if either SWITCH = 1 (windowing case, see
Section 2.6.1) or color key = 1, palette graphics are displayed (overlay or VGA depending on multiplex-
control register 2 bit 7) instead of direct-color data. Both functions must be correctly set for proper operation.
2.7
Overscan
The Viewpoint palette provides the capability to produce a custom screen border using the overscan
function. The overscan function is controlled by general-control-register (GCR) bits 6 and 7. GCR bit 6 is
used to enable overscan, and GCR bit 7 specifies whether the overscan area is defined by OVS or by internal
circuitry. The overscan color is user-programmable by writing to the overscan color red, green, and blue
registers in the indirect register map.
If the overscan function is enabled (GCR6 = logic 1) and the OVS terminal is used to control the area of
overscan (GCR7 = logic 0), then overscan color is displayed any time that OVS is high and BLANK is low
(active). Note that BLANK is the internal blank signal and can either be generated from VGABL or SYSBL
depending on the mode selected. If the Viewpoint internal circuitry is chosen to generate overscan
(GCR7 = logic 1), then internal vertical and horizontal SYNC and BLANK are used to define the overscan
display area. Whenever BLANK is active and vertical and horizontal SYNC are inactive, overscan is
displayed. Internally generated timing may not work with some CRT monitors.
If overscan is enabled, then the blanking pedestal is imposed on the analog outputs when OVS is high and
BLANK is low. If overscan is disabled, then the blanking pedestal occurs when BLANK is low. BLANK can
be either SYSBL or VGABL depending on the state of multiplex-control register 2 bit 7.
If VGA is disabled, OVS is sampled on the falling edge of VCLK and then resampled on the rising edge of
RCLK before being passed to the RCLK and dot clock pipeline delay. If VGA is enabled, then OVS is
sampled on the rising edge of CLK0 and passed to dot clock pipeline delay. In this way, the video timing
relationship is maintained since the same method and pipeline delay are applied to the SYSBL and VGABL
signals.