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參數(shù)資料
| 型號： | TVP5031TQFP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | NTSC/PAL VIDEO DECODER |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數(shù)： | 34/85頁 |
| 文件大?。?/td> | 378K |
| 代理商： | TVP5031TQFP |
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2–18
When a slave does not acknowledge the slave address, the data line must be left high by the slave. The master can
then generate a stop condition to abort the transfer.
If a slave does acknowledge the slave address but some time later in the transfer cannot receive any more data bytes,
the master must again abort the transfer. This is indicated by the slave generating the not acknowledge on the first
byte to follow. The slave leaves the data line high and the master generates the stop condition.
If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating
an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter must release the data line
to allow the master to generate a stop or repeated start condition.
2.6.1.2 I
2
C Write Operation
Data transfers occur utilizing the following illustrated formats.
An I
2
C master initiates a write operation to TVP5031 by generating a start condition followed by TVP5031s I
2
C
address 101110X , the X in the TVP5031 address is 0 when VC3 terminal is tied low and is 1 when VC3 terminal is
tied high, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving an acknowledge from TVP5031,
the master presents the subaddress of the register, or the first of a block of registers it wants to write, followed by one
or more bytes of data, MSB first. TVP5031 acknowledges each byte after completion of each transfer. The I
2
C master
terminates the write operation by generating a stop condition.
STEP 1
I2C Start (master)
0
S
STEP 2
7
6
5
4
3
2
1
0
I2C General address (master)
1
0
1
1
1
0
X
0
STEP 3
I2C Acknowledge (slave)
9
A
STEP 4
I2C Write register address (master)
7
6
5
4
3
2
1
0
addr
addr
addr
addr
addr
addr
addr
addr
STEP 5
I2C Acknowledge (slave)
9
A
STEP 6
I2C Write data (master)
7
6
5
4
3
2
1
0
Data
Data
Data
Data
Data
Data
Data
Data
STEP 7
I2C Acknowledge (slave)
Repeat steps 6 and 7 until all data has been written
9
A
STEP 8
I2C Stop (master)
0
P
2.6.1.3 I
2
C Read Operation
The read operation consists of two phases. The first phase is the address phase. In this phase, an I
2
C master initiates
a write operation to TVP5031 by generating a start condition followed by TVP5031s I
2
C address 101110X, in MSB
first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledge from TVP5031, the master
presents the subaddress of the register, or the first of a block of registers it wants to read. After the cycle is
acknowledged, the master terminates the cycle immediately by generating a stop condition. The second phase is the
data phase. In this phase, a I
2
C master initiates a read operation to TVP5031 by generating a start condition followed
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TVP5040 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL Digital Video Decoder With Macrovision Detection |
| TVP5040CPFP | 功能描述:IC NTSC/PAL VIDEO DECODER 80TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| TVP5040CPFPG4 | 功能描述:IC NTSC/PAL VIDEO DECODER 80TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| TVP5040EVM | 制造商:Texas Instruments 功能描述:EVAL BD TVP5040EVM USER S GUIDE - Bulk |
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