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參數(shù)資料
| 型號： | TVP5031TQFP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | NTSC/PAL VIDEO DECODER |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數(shù)： | 53/85頁 |
| 文件大小： | 378K |
| 代理商： | TVP5031TQFP |
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2–37
2.11.4 Miscellaneous Control
Address
03h
7
6
5
4
3
2
1
0
GPCL function
select
PALI and FID func-
tion select
Y U/V output
enable
HSYN, VSYN, AVID,
FID, PALI output enable
Reserved
Vertical blanking
on/off
Clock output enable
GPCL terminal function select:
00 = GPCL is logic 0 output (default)
01 = GPCL is logic 1 output
10 = GPCL is vertical blank output
11 = GPCL is external sync lock control input
When GPCL is configured as a vertical blank output, the vertical blanking on/off bit is used to activate the output. When
GPCL is configured as a sync lock control, it can be used to force the internal PLLs to their normal settings. This
causes all clocks and synchronization signals to assume nominal values. The sync lock control input is active high.
PALI terminal and FID terminal function select:
0 = PALI outputs PAL indicator signal and terminal FID outputs field ID signal (default)
1 = PALI outputs horizontal lock indicator (HLK) and terminal FID outputs vertical lock indicator (VLK)
Y U/V output enable:
0 = Y U/V high impedance (default)
1 = Y U/V active
Horizontal sync (HSYN), vertical sync (VSYN), active video indicator (AVID), PALI, and FID output enables:
0 = HSYN, VSYN, AVID, PALI, and FID are high impedance
1 = HSYN, VSYN, AVID, PALI, and FID are active
This bit is default to 0 after reset if the AVID terminal is pulled down during reset or default to 1 if the AVID terminal
is pulled up during reset.
Vertical blanking on/off control:
0 = Vertical blanking off (default)
1 = Vertical blanking on
Clock enable:
0 = SCLK and PCLK outputs are high impedance
1 = SCLK and PCLK outputs are enabled
This bit is default to 0 after reset if the PREF terminal is pulled down during reset or default to 1 if the AVID is pulled
up during reset.
Table 2–14. Digital Output Control
REG C2,
BIT 2
(VDPOE)
X
High impedance
OEB
PIN
AVID PIN
REG 03,
BIT 4
(TVPOE)
X
YUV OUTPUT
NOTES
1
X
At all times
After reset and before YUV output enable bits are programmed.
TVPOE bit is default to 1 and VDPOE bit is to 1
After reset and before YUV output enable bits are programmed.
TVPOE bit is default to 0 and VDPOE bit is to 1
0
1 during reset
X
X
Active after reset
0
0 during reset
X
X
High impedance
after reset
0
0
0
X
X
X
0
X
1
X
0
1
High impedance
High impedance
Active
After both YUV output enable bits are programmed
After both YUV output enable bits are programmed
After both YUV output enable bits are programmed
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