參數(shù)資料
型號(hào)： TVP5031TQFP
廠商： Texas Instruments, Inc.
英文描述： NTSC/PAL VIDEO DECODER
中文描述： NTSC / PAL視頻解碼器
文件頁(yè)數(shù)： 38/85頁(yè)
文件大小： 378K
代理商： TVP5031TQFP
2–22
2.6.1.9 Read Phase 2:
STEP 7
I2C Start (master)
0
S
STEP 8
I2C General address (master)
7
6
5
4
3
2
1
0
1
0
1
1
1
0
X
1
STEP 9
I2C Acknowledge (slave)
7
A
STEP 10
I2C Read data (slave)
7
6
5
4
3
2
1
0
Data
Data
Data
Data
Data
Data
Data
Data
STEP 11
I2C Acknowledge (master)
7
A
Repeat STEP 10 and STEP 11 for all but the last byte read from program RAM.
STEP 12
I2C Read Data (slave)
7
6
5
4
3
2
1
0
Data
Data
Data
Data
Data
Data
Data
Data
STEP 13
I2C Not acknowledge (master)
9
A
STEP 14
I2C Stop (master)
0
P
2.6.2
Parallel Host Interface A
Parallel host interface A is compatible with Video Electronics Standards Association (VESA) Video Module Interface
(VMI) proposal version 1.4 mode A. The terminal descriptions are defined in Table 2–4.
Table 2–4. Parallel Host Interface A Terminal Description
TERMINAL
SIGNAL
TYPE
DESCRIPTION
A[1:0]
HA[1:0]
I
Address bus from host
D[7:0]
HD[7:0]
I/O
Bidirectional data bus
VC3
CS
I
Chip select, active low
VC2
DS
I
Data strobe, active low
VC1
RD/WR
I
Read, active high Write, active low
VC0
DTACK
O
Data acknowledge
INTREQ
INTREQ
O
Interrupt request,
Open drain by default, active low, pullup resistor required
Can be configured, subaddress C2, as a conventional CMOS buffer, active high, no pullup required.
Parallel host interface A timing is shown in Figure 2–27. The cycle is initiated by the host when VC2-DS transitions
low. The TVP5031 responds by pulling VC0-DTACK low to indicate data has been received or that the requested data
is present on the bus. The host then completes the cycle by pulling VC2-DS high. Once the host has completed the
cycle, the TVP5031 sets VC0-DTACK to high impedance. A pullup is required to pull VC0-DTACK high to indicate
the operation is complete.
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