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參數(shù)資料
| 型號： | TVP5031TQFP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | NTSC/PAL VIDEO DECODER |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數(shù)： | 72/85頁 |
| 文件大?。?/td> | 378K |
| 代理商： | TVP5031TQFP |
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2.11.45 FIFO Control
Address
B6h
7
6
5
4
3
2
1
0
FIFO Control (R/W)
Reserved
CCD
Reset
Read in
Progress
RAM Test
TTX PHI Output Enable
FIFO Reset
FIFO Reset
When a 1 is written to this register bit, the FIFO is flushed. This is done by clearing the read
and write pointers to zero, clearing the Tx count to zero and clearing all status flags. This
bit is automatically cleared back to 0.
TTX PHI Output Enable A 1 in this register enables access to the teletext data in the FIFO through the parallel host
port and disables access from the output formatter. A 0 disables access from the parallel
host and enables access from the output formatter. The default value is one.
RAM TEST
Setting this bit high allows the micro to write data into the FIFO. In this mode, data from the
TXP is ignored. This allows the micro to test the RAM by writing and reading test patterns.
The default value is zero.
Read in Progress
This bit indicates that the first byte of a teletext transaction has been read, but the last byte
has not been read. This bit can be used to verify data alignment as it is read from the FIFO.
CCD Reset
When a 1 is written to this register bit, the closed caption register is reset. Also, the status
flag is cleared to 0. This bit is automatically cleared back to 0.
2.11.46 FIFO RAM Test
Address
B7h
7
6
5
4
3
2
1
0
FIFO RAM Test (W)
FIFO RAM test register provides diagnostic capability into the internal teletext FIFO. This register can be written
sequentially with a block of data. The data is read back using the Teletext FIFO data register at address B0h to verify
the correct operation of the FIFO.
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| TVP5031CPFP | Color Decoder Circuit |
| TVR4J | TOSHIBA Fast Recovery Diode Silicon Diffused Type High Speed Rectifier Applications (fast recovery) |
| TVR4N | TOSHIBA Fast Recovery Diode Silicon Diffused Type High Speed Rectifier Applications (fast recovery) |
| TVU001 | 14 pin DIP, 5.0 Volt, HCMOS/TTL, Clock Oscillator |
| TVU002 | 14 pin DIP, 5.0 Volt, HCMOS/TTL, Clock Oscillator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP5040 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL Digital Video Decoder With Macrovision Detection |
| TVP5040CPFP | 功能描述:IC NTSC/PAL VIDEO DECODER 80TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| TVP5040CPFPG4 | 功能描述:IC NTSC/PAL VIDEO DECODER 80TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| TVP5040EVM | 制造商:Texas Instruments 功能描述:EVAL BD TVP5040EVM USER S GUIDE - Bulk |
| TVP5145 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NTSC/PAL/SECAM/Component Digital Video Decoder With Macrovision(TM) Detection |
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