11
5.5.5 Processor Revision Identifier (PRId) Register (15) ................................................................. 149
5.5.6 Config Register (16)................................................................................................................... 150
5.5.7 Load Linked Address (LLAddr) Register (17).......................................................................... 151
5.5.8 Cache Tag Registers (TagLo (28) and TagHi (29)) .................................................................. 152
5.5.9 Virtual-to-Physical Address Translation.................................................................................. 153
5.5.10 TLB Misses ............................................................................................................................... 155
5.5.11 TLB Instructions....................................................................................................................... 155
CHAPTER 6 EXCEPTION PROCESSING........................................................................................... 157
6.1
6.2
6.3
HOW EXCEPTION PROCESSING WORKS........................................................................ 157
PRECISION OF EXCEPTIONS............................................................................................. 158
EXCEPTION PROCESSING REGISTERS ........................................................................... 159
6.3.1 Context Register (4)................................................................................................................... 160
6.3.2 BadVAddr Register (8)............................................................................................................... 161
6.3.3 Count Register (9)...................................................................................................................... 161
6.3.4 Compare Register (11)............................................................................................................... 162
6.3.5 Status Register (12) ................................................................................................................... 162
6.3.6 Cause Register (13).................................................................................................................... 165
6.3.7 Exception Program Counter (EPC) Register (14).................................................................... 167
6.3.8 WatchLo (18) and WatchHi (19) Registers............................................................................... 168
6.3.9 XContext Register (20)............................................................................................................... 169
6.3.10 Parity Error Register (26)......................................................................................................... 170
6.3.11 Cache Error Register (27)........................................................................................................ 171
6.3.12 ErrorEPC Register (30) ............................................................................................................ 171
DETAILS OF EXCEPTIONS ................................................................................................. 173
6.4.1 Exception Types......................................................................................................................... 173
6.4.2 Exception Vector Locations...................................................................................................... 173
6.4.3 Priority of Exceptions................................................................................................................ 176
6.4.4 Cold Reset Exception ................................................................................................................ 177
6.4.5 Soft Reset Exception ................................................................................................................. 178
6.4.6 NMI Exception ............................................................................................................................ 179
6.4.7 Address Error Exception........................................................................................................... 180
6.4.8 TLB Exceptions.......................................................................................................................... 181
6.4.9 Cache Error Exception............................................................................................................... 184
6.4.10 Bus Error Exception................................................................................................................. 185
6.4.11 System Call Exception............................................................................................................. 186
6.4.12 Breakpoint Exception .............................................................................................................. 186
6.4.13 Coprocessor Unusable Exception.......................................................................................... 187
6.4.14 Reserved Instruction Exception ............................................................................................. 188
6.4.15 Trap Exception ......................................................................................................................... 188
6.4.16 Integer Overflow Exception..................................................................................................... 189
6.4.17 Watch Exception ...................................................................................................................... 189
6.4.18 Interrupt Exception .................................................................................................................. 190
EXCEPTION PROCESSING AND SERVICING FLOWCHARTS....................................... 191
6.4
6.5