參數(shù)資料
型號： UPD30550F2-300-NN1
廠商： NEC Corp.
英文描述： VR5500⑩ 64-/32-BIT MICROPROCESSOR
中文描述： VR5500⑩64-/32-BIT微處理器
文件頁數(shù)： 9/27頁
文件大小： 569K
代理商： UPD30550F2-300-NN1
Data Sheet U15700EJ1V0DS
9
μ
PD30550
(2) Initialization interface signals
(1/2)
Pin Name
I/O
Function
DivMode(2:0)
Division mode
These signals set the division ratio of PClock and SysClock as follows:
111: 5.5
110: 5
101: 4.5
100: 4
011: 3.5
010: 3
001: 2.5
000: 2
Set the input levels of these signals before a power-on reset. Make sure that the levels of these
signals do not change while the V
R
5500 is operating.
BigEndian
Input
Endian mode
This signal sets the byte ordering for addressing.
1: Big endian
0: Little endian
Set the input level of this signal before a power-on reset. Make sure that the level of this signal
does not change during VR5500 operation.
BusMode
Input
Bus mode
This signal sets the bus width of the system interface.
1: 64 bits
0: 32 bits
Set the input level of this signal before a power-on reset. Make sure that the level of this signal
does not change during VR5500 operation.
TIntSel
Input
Interrupt source select
This signal sets the interrupt source to be assigned to the IP7 bit of the Cause register.
1: Timer interrupt
0: Int5# input and external write request (SysAD5)
Set the input level of this signal before a power-on reset. Make sure that the level of this signal
does not change during VR5500 operation.
DisDValidO#
Input
ValidOut# delay enable
1: ValidOut# is active even while the address cycle is stalled
0: ValidOut# is active during the address issuance cycle only
Set the input level of this signal before a power-on reset. Make sure that the level of this signal
does not change during VR5500 operation.
DWBTrans#
Input
Doubleword block transfer enable (valid in 32-bit bus mode only)
1: Disabled
0: Enabled
Set the input level of this signal before a power-on reset. Make sure that the level of this signal
does not change during VR5500 operation.
Remark
1: High level, 0: Low level
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