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參數(shù)資料
| 型號： | UPD44323362F1-C40-FJ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 1M-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE |
| 中文描述： | 32兆位CMOS同步快速靜態(tài)RAM的100萬字的36位HSTL接口/寄存器間/晚寫 |
| 文件頁數(shù)： | 5/28頁 |
| 文件大小： | 252K |
| 代理商： | UPD44323362F1-C40-FJ1 |
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5
Data Sheet M16379EJ4V0DS
μ
PD44323362
Programmable Impedance / Power Up Requirements
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V
SS
to allow for the SRAM to
adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by
the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between 175
ohm and 350 ohm. Periodic readjustment of the output driver impedance is necessary as the impedance is greatly
affected by drifts in supply voltage and temperature. The impedance update of the output driver occurs only when the
SRAM is in high impedance. Write and Deselect operations will synchronously switch the SRAM into and out of high
impedance, therefore, triggering an update. Power up requirements for the SRAM are that V
DD
must be powered
before or simultaneously with V
DD
Q followed by V
REF
; inputs should be powered last. The limitation on V
DD
Q is that it
must not exceed V
DD
during power up. In order to guarantee the optimum internally regulated supply voltage, the
SRAM requires 4096 clock cycles of power-up time after V
DD
reaches its operating range. And CID impedance is not
updated during the clock stopped.
Sleep Mode
Sleep Mode is enabled by switching asynchronous signal ZZ High. When the SRAM is in Sleep Mode, the output
will go to a high impedance state and the SRAM will draw standby current. SRAM data will be preserved and a
recovery time (t
ZZR
) is required before the SRAM resumes normal operation. And CID impedance is not updated
during the sleep mode.
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| UPD44323362 | 32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 1M-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE |
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| UPD44324082F5-E33-EQ2 | 36M-BIT DDRII SRAM 2-WORD BURST OPERATION |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44324182BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:RENUPD44324182BF5-E40-FQ1-A 36M-BIT(2M-W |
| UPD44324185BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324362BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324362BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324365BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
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