參數(shù)資料
型號： UPD44323362F1-C40-FJ1
廠商： NEC Corp.
英文描述： 32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 1M-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
中文描述： 32兆位CMOS同步快速靜態(tài)RAM的100萬字的36位HSTL接口/寄存器間/晚寫
文件頁數(shù)： 6/28頁
文件大?。?/td> 252K
代理商： UPD44323362F1-C40-FJ1
6
Data Sheet M16379EJ4V0DS
μ
PD44323362
Synchronous Truth Table
ZZ
/SS /SW /SBa /SBb /SBc /SBd
Mode
DQa1 to DQa9 DQb1 to DQb9 DQc1 to DQc9 DQd1 to DQd9
Power
L
H
×
×
×
×
×
Not selected
High-Z
High-Z
High-Z
High-Z
Active
L
L
H
×
×
×
×
Read
Dout
Dout
Dout
Dout
Active
L
L
L
L
L
L
L
Write
Din
Din
Din
Din
Active
L
L
L
L
H
H
H
Write
Din
High-Z
High-Z
High-Z
Active
L
L
L
H
L
L
L
Write
High-Z
Din
Din
Din
Active
H
×
×
×
×
×
×
Sleep Mode
High-Z
High-Z
High-Z
High-Z
Standby
Remark
×
: Don't care
Output Enable Truth Table
Mode
/G
DQ
Read
L
Dout
Read
H
High-Z
Sleep (ZZ = H)
×
High-Z
Write (/SW = L)
×
High-Z
Deselect (/SS = H)
×
High-Z
Mode Select (I/O)
Note 1
M1
M2
Mode
V
SS
V
DD
Single Differential Clock (K, /K), R/R Mode
Note 2
Notes 1.
This device only supports Single Differential Clock, R/R Mode. Mode Select Pins (M1, M2) are to be tied
to either V
DD
or V
SS
.
2.
R/R: Registered Input / Registered Output
Mode Select (Output Buffer)
ZQ
Mode
Note
IZQ
×
RQ
Controlled impedance push-pull output buffer mode
1
V
DD
Push-pull output buffer mode
2
Notes 1.
See figure.
ZQ
2.
See figure.
ZQ
V
DD
相關(guān)PDF資料
PDF描述
UPD44323362 32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 1M-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
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參數(shù)描述
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UPD44324362BF5-E40-FQ1 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA
UPD44324362BF5-E40-FQ1-A 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA
UPD44324365BF5-E40-FQ1 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA
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