參數(shù)資料
型號: UPD45128163-A75L
廠商: Elpida Memory, Inc.
英文描述: 128M-bit Synchronous DRAM 4-bank, LVTTL
中文描述: 128兆位同步DRAM 4銀行,LVTTL
文件頁數(shù): 20/86頁
文件大?。?/td> 821K
代理商: UPD45128163-A75L
Data Sheet E0344N10 (Ver. 1.0)
20
μ
PD45128163
7. Mode Register
WT = 1
1
2
4
8
R
R
R
R
1
0
0
0
0
JEDEC Standard Test Set (refresh counter test)
BL
WT
LTMODE
0
0
1
x
x
Burst Read and Single Write
(for Write Through Cache)
0
1
Use in future
V
V
V
V
V
V
1
V
1
x
x
x
Vender Specific
BL
WT
LTMODE
0
0
0
0
0
Mode Register Set
V = Valid
x = Don’t care
WT = 0
1
2
4
8
R
R
R
Full page
Bits2-0
000
001
010
011
100
101
110
111
Burst length
Sequential
Interleave
0
1
Wrap type
/CAS latency
R
R
2
3
R
R
R
R
Bits6-4
000
001
010
011
100
101
110
111
Latency
mode
0
0
A0
A1
A2
A3
A4
A5
A7
A6
A8
A9
A10
A11
BA1
(A12)
BA0
(A13)
A0
A1
A2
A3
A4
A5
A7
A6
A8
A9
A10
A11
BA1
(A12)
BA0
(A13)
A0
A1
A2
A3
A4
A5
A7
A6
A8
A9
A10
A11
BA1
(A12)
BA0
(A13)
A0
A1
A2
A3
A4
A5
A7
A6
A8
A9
A10
A11
BA1
(A12)
BA0
(A13)
A0
A1
A2
A3
A4
A5
A7
A6
A8
A9
A10
A11
BA1
(A12)
BA0
(A13)
x
x
x
x
0
0
Remark
R : Reserved
CLK
CKE
/CS
/RAS
/CAS
/WE
A0 - A11,
BA0(13), BA1(A12)
Mode Register Set
Mode Register Set Timing
相關(guān)PDF資料
PDF描述
UPD45128163G5-A10LT-9JF 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
UPD45128163G5-A80T-9JF 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
UPD45128163G5-A75T-9JF 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
UPD45128163G5-A10T-9JF 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
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