參數(shù)資料
型號(hào)： UPD4616112F9-B85LX-BC2
廠商： NEC Corp.
英文描述： 16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
中文描述： 1,600位CMOS移動(dòng)指明內(nèi)存100萬字由16位溫度范圍
文件頁數(shù)： 15/32頁
文件大?。?/td> 212K
代理商： UPD4616112F9-B85LX-BC2
Data Sheet M15794EJ2V0DS
15
μ
PD4616112-X
Write Cycle (B version)
Parameter
Symbol
μ
PD4616112-B85LX
μ
PD4616112-B95LX
Unit
Note
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
85
10,000
95
10,000
ns
1
Identical address write cycle time
t
WC1
85
10,000
95
10,000
ns
2
Address skew time
t
SKEW
10
20
ns
3
/CS to end of write
t
CW
40
50
ns
4
/LB, /UB to end of write
t
BW
30
35
ns
Address valid to end of write
t
AW
35
45
ns
Write pulse width
t
WP
30
35
ns
Write recovery time
t
WR
20
20
ns
5
/CS pulse width
t
CP
10
10
ns
Address setup time
t
AS
0
0
ns
Byte write hold time
t
BWH
20
20
ns
Data valid to end of write
t
DW
20
25
ns
Data hold time
t
DH
0
0
ns
/OE to output in low impedance
t
OLZ
5
5
ns
/WE to output in high impedance
t
WHZ
25
25
ns
/OE to output in high impedance
t
OHZ
25
25
ns
Output active from end of write
t
OW
5
5
ns
Notes 1.
One write cycle (t
WC
) must satisfy the minimum value (t
WC(MIN.)
) and the maximum value (t
WC(MAX.)
= 10
μ
s).
t
WC
indicates the time from the /CS low level input point or address change start point, whichever is after,
to the /CS high level input point or the next address change start point, whichever is earlier. As a result,
there are the following four conditions for t
WC
.
1) Time from address change start point to /CS high level input point
2) Time from address change start point to next address change start point
3) Time from /CS low level input point to next address change start point
4) Time from /CS low level input point to /CS high level input point
2.
The identical address read cycle time (t
WC1
) is the cycle time of one write cycle when performing continuous
write operations with the address fixed and /CS low level, changing /LB and /UB at the same time, and
toggling /WE, as well as when performing a continuous write toggling /LB and /UB. Make settings so that
the sum (t
WC
) of the identical address write cycle times (t
WC1
) is 10
μ
s or less.
3.
t
SKEW
indicates the following three types of time depending on the condition.
1) When switching /CS from high level to low level, t
SKEW
is the time from the /CS low level input point until
the next address is determined.
2) When switching /CS from low level to high level, t
SKEW
is the time from the address change start point to
the /CS high level input point.
3) When /CS is fixed to low level, t
SKEW
is the time from the address change start point until the next address
is determined.
Since specs are defined for t
SKEW
only when /CS is active, t
SKEW
is not subject to limitations when /CS is
switched from high level to low level following address determination, or when the address is changed after
/CS is switched from low level to high level.
相關(guān)PDF資料
PDF描述
UPD4616112F9-BC80-BC2 16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT
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UPD4616112-X 16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
UPD4616112F9-BC90-BC2 16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT
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