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參數(shù)資料
| 型號： | UPD4616112F9-BC80-BC2 |
| 廠商： | NEC Corp. |
| 英文描述： | 16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT |
| 中文描述： | 1,600位CMOS移動(dòng)指明內(nèi)存100萬字由16位 |
| 文件頁數(shù)： | 10/32頁 |
| 文件大?。?/td> | 220K |
| 代理商： | UPD4616112F9-BC80-BC2 |
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Data Sheet M15085EJ5V0DS
10
μ
PD4616112
#
#
#
#
Read Cycle (BC version)
Parameter
Symbol
μ
PD4616112-BC80
μ
PD4616112-BC90
Unit
Notes
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
80
10,000
90
10,000
ns
1
Identical address read cycle time
t
RC1
80
10,000
90
10,000
ns
2
Address skew time
t
SKEW
10
20
ns
3
/CS pulse width
t
CP
10
10
ns
Address access time
t
AA
80
90
ns
4
/CS access time
t
ACS
80
90
ns
/OE to output valid
t
OE
35
40
ns
5
/LB, /UB to output valid
t
BA
35
40
ns
Output hold from address change
t
OH
10
10
ns
/CS to output in low impedance
t
CLZ
10
10
ns
/OE to output in low impedance
t
OLZ
5
5
ns
/LB, /UB to output in low impedance
t
BLZ
5
5
ns
/CS to output in high impedance
t
CHZ
25
25
ns
/OE to output in high impedance
t
OHZ
25
25
ns
/LB, /UB to output in high impedance
t
BHZ
25
25
ns
Notes 1.
One read cycle (t
RC
) must satisfy the minimum value (t
RC(MIN.)
) and maximum value (t
RC(MAX.)
= 10
μ
s). t
RC
indicates the time from the /CS low level input point or address change start point, whichever is later, to
the /CS high level input point or the next address change start point, whichever is earlier. As a result,
there are the following four conditions for t
RC
.
1) Time from address change start point to /CS high level input point
2) Time from address change start point to next address change start point
3) Time from /CS low level input point to next address change start point
4) Time from /CS low level input point to /CS high level input point
2.
The identical address read cycle time (t
RC1
) is the cycle time of one read operation when performing
continuous read operations toggling /OE , /LB, and /UB with the address fixed and /CS low level. Perform
settings so that the sum (t
RC
) of the identical address read cycle times (t
RC1
) is 10
μ
s or less.
3.
t
SKEW
indicates the following three types of time depending on the condition.
1) When switching /CS from high level to low level, t
SKEW
is the time from the /CS low level input point until
the next address is determined.
2) When switching /CS from low level to high level, t
SKEW
is the time from the address change start point to
the /CS high level input point.
3) When /CS is fixed to low level, t
SKEW
is the time from the address change start point until the next address
is determined.
Since specs are defined for t
SKEW
only when /CS is active, t
SKEW
is not subject to limitations when /CS is
switched from high level to low level following address determination, or when the address is changed after
/CS is switched from low level to high level.
4.
Regarding t
AA
and t
ACS
, only t
AA
is satisfied during address access (refer to 1) and 2) of
Note 1
), and only
t
ACS
is satisfied during /CS access (refer to 3) of
Note 1
).
5.
Regarding t
BA
and t
OE
, only t
BA
is satisfied if /OE becomes active later than /UB and /LB, and only t
OE
is
satisfied if /UB and /LB become active before /OE.
(address access)
(address access)
(/CS access)
(/CS access)
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