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參數(shù)資料
| 型號(hào)： | UPD4616112F9-BC80-BC2 |
| 廠商： | NEC Corp. |
| 英文描述： | 16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT |
| 中文描述： | 1,600位CMOS移動(dòng)指明內(nèi)存100萬(wàn)字由16位 |
| 文件頁(yè)數(shù)： | 18/32頁(yè) |
| 文件大?。?/td> | 220K |
| 代理商： | UPD4616112F9-BC80-BC2 |
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Data Sheet M15085EJ5V0DS
18
μ
PD4616112
#
Write Cycle Timing Chart 2 (/WE Controlled)
t
CW
t
AW
/CS (Input)
Address (Input)
t
AS
t
WP
/WE (Input)
t
SKEW
t
SKEW
t
AW
t
DW
t
DH
I/O (Input / Output)
t
WR
t
OW
t
AW
t
SKEW
t
CP
t
WHZ
High impedance
High impedance
High impedance
/OE (Input)
t
OHZ
t
OLZ
t
WP
t
AS
t
AS
t
WC
t
WC
t
WC
t
WP
t
WR
t
WR
t
DW
t
DH
t
DW
t
DH
t
SKEW
/CS (Input)
Address (Input)
/WE (Input)
t
DW
t
DH
I/O (Input)
t
SKEW
t
SKEW
High impedance
High impedance
High impedance
t
WC1
t
AS
t
WP
t
WP
t
WR
t
DW
t
DH
t
WC1
/LB, /UB (Input)
t
BW
t
SKEW
t
WC
t
WR
Data in
Data in
Data in
Data in
Data in
High
impedance
High
impedance
Indefinite
data out
Note
Note
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the write cycle time (t
WC
), none of the data can be guaranteed.
Note
If /LB and /UB are changed at the same time with /CS low level and a continuous write operation toggling /WE
is performed, make settings so that the sum (t
WC
) of the identical address write cycle time (t
WC1
) is 10
μ
s or
less.
Remarks 1.
Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
2.
When /WE is at Low, the I/O pins are always high impedance. When /WE is at High, read operation is
executed. Therefore /OE should be at High to make the I/O pins high impedance.
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