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PIC24FV32KA304 FAMILY
DS39995C-page 126
2011-2012 Microchip Technology Inc.
10.2.4.5
Deep Sleep WDT
To enable the DSWDT in Deep Sleep mode, program
the Configuration bit, DSWDTEN (FDS<7>). The
device Watchdog Timer (WDT) need not be enabled for
the DSWDT to function. Entry into Deep Sleep mode
automatically resets the DSWDT.
The DSWDT clock source is selected by the
DSWDTOSC Configuration bit (FDS<4>). The post-
scaler options are programmed by the DSWDTPS<3:0>
Configuration bits (FDS<3:0>). The minimum time-out
period that can be achieved is 2.1 ms and the maximum
is 25.7 days. For more details on the FDS Configuration
register and DSWDT configuration options, refer to
.
10.2.4.6
Switching Clocks in Deep Sleep Mode
Both the RTCC and the DSWDT may run from either
SOSC or the LPRC clock source. This allows both the
RTCC and DSWDT to run without requiring both the
LPRC and SOSC to be enabled together, reducing
power consumption.
Running the RTCC from LPRC will result in a loss of
accuracy in the RTCC of approximately 5 to 10%. If a
more accurate RTCC is required, it must be run from
the SOSC clock source. The RTCC clock source is
selected with the RTCOSC Configuration bit (FDS<5>).
Under certain circumstances, it is possible for the
DSWDT clock source to be off when entering Deep
Sleep mode. In this case, the clock source is turned on
automatically (if DSWDT is enabled), without the need
for software intervention. However, this can cause a
delay in the start of the DSWDT counters. In order to
avoid this delay when using SOSC as a clock source,
the application can activate SOSC prior to entering
Deep Sleep mode.
10.2.4.7
Checking and Clearing the Status of
Deep Sleep
Upon entry into Deep Sleep mode, the status bit,
DPSLP (RCON<10>), becomes set and must be
cleared by the software.
On power-up, the software should read this status bit to
determine if the Reset was due to an exit from Deep
Sleep mode and clear the bit if it is set. Of the four
possible combinations of DPSLP and POR bit states,
three cases can be considered:
Both the DPSLP and POR bits are cleared. In this
case, the Reset was due to some event other
than a Deep Sleep mode exit.
The DPSLP bit is clear, but the POR bit is set; this
is a normal POR.
Both the DPSLP and POR bits are set. This
means that Deep Sleep mode was entered, the
device was powered down and Deep Sleep mode
was exited.
10.2.4.8
Power-on Resets (PORs)
VDD voltage is monitored to produce PORs. Since
exiting from Deep Sleep functionally looks like a POR,
should be
used to distinguish between Deep Sleep and a true POR
event.
When a true POR occurs, the entire device, including
all Deep Sleep logic (Deep Sleep registers: RTCC,
DSWDT, etc.) is reset.
10.2.4.9
Summary of Deep Sleep Sequence
To review, these are the necessary steps involved in
invoking and exiting Deep Sleep mode:
1.
The device exits Reset and begins to execute its
application code.
2.
If DSWDT functionality is required, program the
appropriate Configuration bit.
3.
Select the appropriate clock(s) for the DSWDT
and RTCC (optional).
4.
Enable and configure the DSWDT (optional).
5.
Enable and configure the RTCC (optional).
6.
Write context data to the DSGPRx registers
(optional).
7.
Enable the INT0 interrupt (optional).
8.
Set the DSEN bit in the DSCON register.
9.
Enter Deep Sleep by issuing a PWRSV
#SLEEP_MODE
command.
10. The device exits Deep Sleep when a wake-up
event occurs.
11. The DSEN bit is automatically cleared.
12. Read and clear the DPSLP status bit in RCON,
and the DSWAKE status bits.
13. Read the DSGPRx registers (optional).
14. Once all state related configurations are
complete, clear the RELEASE bit.
15. The application resumes normal operation.