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參數資料
| 型號： | UPD72852AGB-8EU |
| 廠商： | NEC Corp. |
| 英文描述： | IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI |
| 中文描述： | 1個IEEE1394a 2000年的要求400 Mbps的雙端口PHY的大規(guī)模集成電路 |
| 文件頁數： | 16/48頁 |
| 文件大小： | 373K |
| 代理商： | UPD72852AGB-8EU |
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Data Sheet S16725EJ2V0DS
16
μ
PD72852A
3. INTERNAL FUNCTION
3.1 Link Interface
3.1.1 Connection Method
Figure 3-1. PHY/Link Connection Method
Link
PHY
μ
PD72852A
D0-D7
CTL0,CTL1
DIRECT
LPS
LKON
SCLK
LREQ
Note
Note
Clamping to V
DD
provides direct connection to Link.
Clamping to GND connects through isolation barrier to Link.
The isolation barrier connection circuit is described in
3.1.7 Isolation Barrier.
3.1.2 LPS (Link Power Status)
LPS is a function to monitor the On/Off status of the Link power supply. After 1.2
μ
sec or more, LPS is Low, the
PHY/Link is reset and D and CTL are output Low (when the isolation barrier is Hi-Z). After 2.5
μ
sec or more, LPS is
Low, moreover, the PHY stops the supply of SCLK and SCLK outputs Low (when the isolation barrier is Hi-Z).
3.1.3 LREQ, CTL0, CTL1 and D0-D7 Pins
LREQ
: Indicates that a request is received from Link.
CTL0, CTL1 : Bi-directional pin which controls the functions between the PHY/Link interface.
D0-D7
: Bi-directional pin which controls the data Transfer/Receive status signal, and the speed code
Transfer/Receive status signal.
3.1.4 SCLK
49.152 MHz clock supplied by PHY for the PHY/Link interface synchronization.
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