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參數(shù)資料
| 型號： | UPD72852AGB-8EU |
| 廠商： | NEC Corp. |
| 英文描述： | IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI |
| 中文描述： | 1個IEEE1394a 2000年的要求400 Mbps的雙端口PHY的大規(guī)模集成電路 |
| 文件頁數(shù)： | 26/48頁 |
| 文件大?。?/td> | 373K |
| 代理商： | UPD72852AGB-8EU |
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Data Sheet S16725EJ2V0DS
26
μ
PD72852A
Acceleration Controller
Table 4-8. Acceleration Controller Request Format
Bit
Type
Content
0
start
Signal that starts a request : 1
1-3
request
110 : Acc Ctrl accelerate controller
4
access address
0: Accelerate disable
1: Accelerate enable
5
stop
End request signal : 0
Table 4-9. Request Type List
Bit
Type
Content
000
ImmReq
Used to acknowledge packet transmit.
When Idle is detected, PHY immediately controls the bus.
001
IsoReq
Used to transmit isochronous packet.
PHY does arbitration after isochronous gap is detected and acquires the bus.
010
PriReq
Used for Cycle master request.
011
FairReq
Fair request.
100
RdReg
PHY register read request.
101
WrReg
PHY register write request.
110
AccCtrl
Disable/enable of arbitration acceleration.
111
-
Unused.
For the Link to execute Priority request and Fair, start the request using LREQ when CTL0, CTL1 becomes idle,
after one clock. When request is acknowledged, the
μ
PD72852A outputs Grant to CTL0, CTL1.
The Link of cycle master uses PriReq to transmit the cycle start packet. IsoReq transmits the isochronous
packet.
IsoReq becomes effective only as follows:
The transmission of the cycle start packet is performed on the same isochronous period as Receive. (The
period until the subaction gap is detected.)
During isochronous packet Transmit or Receive.
The
μ
PD72852A cancels IsoReq with the subaction gap detection or bus reset. To meet the timing, do not
issue the IsoReq to PHY when CRC operation is performed.
The Link cancel method is described later.
After the packet is received, Link issues ImmReq as the acknowledge packet transmission. The purpose is to
prevent another node from detecting subaction gap as ACK_RESPONSE_TIME. The
μ
PD72852A acquires the
bus after packet receive and returns Grant to CTL0, CTL1. When CRC fails, before Link detects Grant, assert 3
Idle cycles to CTL0, CTL1.
When the bus reset is generated, the unprocessed requests are canceled.
The
μ
PD72852A updates the data of the Write request register and the contents of the Read register are
changed. The contents of the register of the specified address are output to the Link as a status transfer in the
Read request register, When the status transmission is interrupted by transmitting/receiving packets, the status
transmission will re-start from the first bit after completing the transmit/receive of the packets.
The bus request (ImmReq, IsoReq, PriReg, FairReq) is completed (in case of ImmReq, IsoReq, when the
subaction gap is detected) when the packet is transmitted or canceled by canceling the bus request.
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