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參數(shù)資料
| 型號： | UPD72852AGB-8EU |
| 廠商： | NEC Corp. |
| 英文描述： | IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI |
| 中文描述： | 1個IEEE1394a 2000年的要求400 Mbps的雙端口PHY的大規(guī)模集成電路 |
| 文件頁數(shù)： | 33/48頁 |
| 文件大?。?/td> | 373K |
| 代理商： | UPD72852AGB-8EU |
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Data Sheet S16725EJ2V0DS
33
μ
PD72852A
Figure 4-7. Link Cancel Timing (After Hold)
00
11
00
ZZ
ZZ
ZZ
ZZ
ZZ
00
00
00
00
ZZ
ZZ
ZZ
ZZ
ZZ
00
ZZ
ZZ
ZZ
00
01
01
00
00
ZZ
ZZ
ZZ
ZZ
00
00
00
00
00
ZZ
PHY CTL0,CTL1
PHY D0-D7
Link CTL0,CTL1
Link D0-D7
4.8 Receive
This section shows the operation when the packet is received from the serial bus.
When the
μ
PD72852A detects DATA_PREFIX on the serial bus, it asserts receive to CTL and all of the D pins
assume the logic value of 1.
The
μ
PD72852A shows the speed code of the transfer rate ahead of the packet using bits D0-D7. Transmitting
the speed code with the speed signal is the protocol of the PHY/Link interface. The speed code is not included in
the CRC calculation.
The
μ
PD72852A continues to assert Receive to CTL until the packet is finally transmitted.
Idle is asserted to CTL, indicating completion of the packet transmission.
Figure 4-8. Receive Timing
00
10
10
10
10
10
00
00
FF
FF
D0
D1
D
n
00
PHY CTL0,CTL1
(Binary)
PHY D0-D7
(Hex)
10
SP
00
00
The packet transfer rate of the serial bus depends on the topology of the bus. The
μ
PD72852A checks if the node
can receive at the faster transfer rate. At this time, DATA_PREFIX
→
DATA_END is transmitted to the
μ
PD72852A.
After DATA_PREFIX is transmitted to the Link, Receive from the serial bus is completed, asserting Idle.
Table 4-14 shows the speed code encoding.
Table 4-14. Speed Encoding
D0-D7
Data rate
Transmitted
Observed
00000000
00xxxxxx
S100
01000000
0100xxxx
S200
01010000
01010000
S400
11111111
11xxxxxx
Data Prefix
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