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參數(shù)資料
| 型號： | UPD75336GK |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機 |
| 文件頁數(shù)： | 37/68頁 |
| 文件大小： | 532K |
| 代理商： | UPD75336GK |
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37
μ
PD75336
Table 8-1 Status after Reset of Each Hardware (2/2)
*
Each display output selects the following V
LCX
as input source.
S12 to S31: V
LC1
COM0 to COM2: V
LC2
COM3: V
LC0
However, the level of each display output varies depending on each display output and V
LCX
external circuit.
Digital port
Output buffer
Output latch
I/O mode register (PMGA, PMGB, PMGC)
Pull-up resistor specification register
(POGA, POGB)
P00 to P03, P10 to P13,
P20 to P23, P30 to P33,
P60 to P63, P70 to P73,
P80 to P83
P40 to P43, P50 to P53
S12 to S31,
COM0 to COM3
BIAS
Bit sequential buffer (BSB0 to BSB3)
Pin status
Interrupt enable flag (IE
×××
)
Priority select register (IPS)
INT0, 1, 2 mode registers (IM0, IM1, IM2)
Interrupt request
flag
(IRQ
×××
)
Hardware
IRQ1, IRQ2, IRQ4
Other than above
Interrupt function
#
RESET Input in Standby
Mode
Undefined
0
0
0
0, 0, 0
OFF
Clear (0)
0
0
Input
High level:
With an on-chip pull-up
resistor
High impedance:
In open-drain
*
Low level:
With an on-chip split resistor
High impedance:
Without an on-chip split
resistor
Held
RESET Input during
Operation
Undefined
0
0
0
0, 0, 0
OFF
Clear (0)
0
0
Input
High level:
With an on-chip pull-up
resistor
High impedance:
In open-drain
*
Low level:
With an on-chip split resistor
High impedance:
Without an on-chip split
resistor
Undefined
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