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135
μ
PD75517(A)
5.4 MULTIPLE INTERRUPT PROCESSING CONTROL
The
μ
PD75517(A) can handle multiple interrupts by either of the following methods.
(1) Multiple interrupt processing by a high-order interrupt
In this method, the
μ
PD75517(A) selects an interrupt source among multiple interrupt sources, enabling
double interrupt processing.
That is, the high-order interrupt specified by the interrupt priority specification register (IPS) is enabled
when the processing status is 0 or 1. Other interrupts (interrupts lower than the specified high-order
interrupt) are enabled only when the status is 0. (See
Fig. 5-6
and
Table 5-3
.)
Fig. 5-6 Multiple Interrupt Processing by a High-Order Interrupt
Table 5-3 Interrupt Processing Statuses of IST1 and IST0
IST1 and IST0 are saved with the remaining PSW in the stack memory when an interrupt is accepted and
the status of IST0 and IST1 changes to a status one level higher. When an RETI instruction is executed,
the former values of IST0 and IST1 are returned.
Normal
processing
(Status 0)
Low- or high-order
interrupt processing
(Status 1)
High-order
interrupt
processing
(Status 2)
Interrupt is disabled.
IPS setting
Interrupt is enabled.
Low- or high-order
interrupt occurrence
High-order
interrupt
occurrence
IST1
IST0
CPU operation
Interrupts that can be accepted
IST0
IST1
0
0
1
1
0
1
0
1
Is processing the normal
program.
Is processing a low- or high-
order interrupt.
Is processing a high-order
interrupt.
All
Only high-order interrupts
No
1
0
–
0
1
–
Processing
status
After acceptance
Status 0
Status 1
Status 2
This status is disabled.