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參數(shù)資料
| 型號(hào)： | UPD75517GF |
| 廠商： | NEC Corp. |
| 英文描述： | 4 BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁(yè)數(shù)： | 91/180頁(yè) |
| 文件大?。?/td> | 1596K |
| 代理商： | UPD75517GF |
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91
μ
PD75517(A)
Fig. 4-36 Format of Serial Bus Interface Control Register (SBIC) (2/3)
Bus release trigger bit (W)
Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or after serial
transfer.
Command trigger bit (W)
Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or after serial
transfer.
Bus release detection flag (R)
Command detection flag (R)
Acknowledge trigger bit (W)
Cautions 1.
Never set ACKT before or during serial transfer.
ACKT cannot be cleared by software.
Before setting ACKT, set ACKE = 0.
2.
3.
Acknowledge enable bit (R/W)
Control bit for bus release signal (REL) trigger output.
By setting RELT = 1, the SO0 latch is set to 1. Then the RELT bit is automatically cleared to 0.
RELT
Condition for being set (RELD = 1)
The bus release signal (REL) is detected.
RELD
Condition for being cleared (RELD = 0)
1
2
3
4
The transfer start instruction is executed.
The RESET signal is entered.
CSIE0 = 0 (See
Fig. 4-35
.)
SVA does not match SIO0 when an address is
received.
Control bit for command signal (CMD) trigger output.
By setting CMDT = 1, the SO0 latch is cleared to 0. Then the CMDT bit is automatically cleared to 0.
CMDT
Condition for being set (CMDD = 1)
The command signal (CMD) is detected.
CMDD
Condition for being cleared (CMDD = 0)
1
2
3
4
The transfer start instruction is executed.
The bus release signal (REL) is detected.
The RESET signal is entered.
CSIE0 = 0 (See
Fig. 4-35
.)
When set after transfer, ACK is output in phase with the next SCK0. After ACK signal output, this bit is auto-
matically cleared to 0.
ACKT
Disables automatic output of the acknowledge signal (ACK). (Output by ACKT is possible.)
ACKE
0
1
When set before transfer
When set after transfer
ACK is output in phase with the 9th clock of SCK0.
ACK is output in phase with SCK0 immediately following set
instruction execution.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD7554AG-597-E2 | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7554AG-597-E2-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7554AG-603-E2 | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7554AG-603-E2-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7554AG-611-E2 | 制造商:Renesas Electronics Corporation 功能描述: |
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