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CHAPTER 1 OUTLINE
32
User
’
s Manual U11302EJ4V0UM
1.8 Overview of Functions
ROM
Mask ROM
One-time
PROM
32 KB
Note 1
40 KB
Note 1
48 KB
60 KB
60 KB
Note 2
High-speed RAM
1024 bytes
Expansion RAM
–
1024 bytes
1024 bytes
Note 3
Buffer RAM
64 bytes
VFD display RAM
80 bytes
General-purpose registers
8 bits x 8 x 4 banks
With main system
clock selected
0.4
μ
s/0.8
μ
s/1.6
μ
s/3.2
μ
s/6.4
μ
s (when operated at 5.0 MHz)
With subsystem
clock selected
122
μ
s (when operated at 32.768 kHz)
16-bit operation
Multiply/divide (8 bits x 8 bits, 16 bits
÷
8 bits)
Bit manipulation (set, reset, test, and Boolean operation)
BCD adjust, and other related operations
I/O ports (including VFD pins)
Total:
74 pins
2 pins
27 pins
5 pins
24 pins
16 pins
CMOS input:
CMOS I/O:
N-ch open-drain I/O:
P-ch open-drain I/O:
P-ch open-drain output:
VFD controller/driver
Total of display output:
Segments:
Digits:
53 pins
9 to 40 pins
2 to 16 pins
A/D converter
8-bit resolution x 8 channels
Power supply voltage: AV
DD
= 4.0 to 5.5 V
Serial interface
3-wire serial I/O/SBI/2-wire serial I/O mode selection
possible:
3-wire serial I/O mode (maximum 64-byte on-chip automatic
transmit/receive function): 1 channel
1 channel
Notes 1.
The initial value of the internal memory size switching register (IMS) in the
μ
PD780204A and 780205A
is fixed to CFH (60 KB), regardless of the internal memory capacity. Therefore, set the values shown
below for each product before use.
μ
PD780204A: C8H (32 KB)
μ
PD780205A: CAH (40 KB)
2.
32, 40, 48, or 60 KB can be selected by the internal memory size switching register (IMS).
3.
0 or 1024 bytes can be selected by the internal expansion RAM size switching register (IXS).
Item
Part Number
Internal
memory
Instruction set
Minimum
instruction
execution
time
μ
PD780204
μ
PD780204A
μ
PD780205
μ
PD780205A
μ
PD780206
μ
PD780208
μ
PD78P0208