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CHAPTER 20 INSTRUCTION SET
387
User’s Manual U11302EJ4V0UM
Instruc- Mnemonic
tion
Group
Operands
Bytes
Operation
MOVW
rp, #word
3
6
–
rp
←
word
(saddrp)
←
word
sfrp
←
word
AX
←
(saddrp)
(saddrp)
←
AX
AX
←
sfrp
sfrp
←
AX
AX
←
rp
rp
←
AX
AX
←
(addr16)
(addr16)
←
AX
AX
rp
A, CY
←
A+byte
(saddr), CY
←
(saddr)+byte
A, CY
←
A+r
r, CY
←
r+A
A, CY
←
A+(saddr)
A, CY
←
A+(addr16)
A, CY
←
A+(HL)
A, CY
←
A+(HL+byte)
A, CY
←
A+(HL+B)
A, CY
←
A+(HL+C)
A, CY
←
A+byte+CY
(saddr), CY
←
(saddr)+byte+CY
A, CY
←
A+r+CY
r, CY
←
r+A+CY
A, CY
←
A+(saddr)+CY
A, CY
←
A+(addr16)+CY
A, CY
←
A+(HL)+CY
A, CY
←
A+(HL+byte)+CY
A, CY
←
A+(HL+B)+CY
A, CY
←
A+(HL+C)+CY
saddrp, #word
4
8
10
sfrp, #word
4
–
10
AX, saddrp
2
6
8
saddrp, AX
2
6
8
AX, sfrp
2
–
8
sfrp, AX
2
–
8
AX, rp
Note 3
1
4
–
rp, AX
Note 3
1
4
–
AX, !addr16
3
10
12
!addr16, AX
3
10
12
XCHW
AX, rp
Note 3
1
4
–
ADD
A, #byte
2
4
–
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
saddr, #byte
3
6
8
A, r
Note 4
2
4
–
r, A
2
4
–
A, saddr
2
4
5
A, !addr16
3
8
9
A, [HL]
1
4
5
A, [HL+byte]
2
8
9
A, [HL+B]
2
8
9
A, [HL+C]
2
8
9
ADDC
A, #byte
2
4
–
saddr, #byte
3
6
8
A, r
Note 4
2
4
–
r, A
2
4
–
A, saddr
2
4
5
A, !addr16
3
8
9
A, [HL]
1
4
5
A, [HL+byte]
2
8
9
A, [HL+B]
2
8
9
A, [HL+C]
2
8
9
Notes 1.
When the internal high-speed RAM area is accessed or an instruction with no data access.
2.
When an area except the internal high-speed RAM area is accessed.
3.
Only when rp = BC, DE, or HL
4.
Except r = A
Remark
One instruction clock cycle is one cycle of the CPU clock (f
CPU
) selected by the processor clock control
register (PCC).
Z
AC CY
Note 2
Note 1
Clocks
Flag
16-bit
data
transfer
8-bit
operation