μPD78F920x
參數(shù)資料
型號(hào): UPD78F9201MA-CAC-A
廠商: Renesas Electronics America
文件頁數(shù): 123/158頁
文件大?。?/td> 0K
描述: MCU 8BIT 2KB FLASH 128B RAM
標(biāo)準(zhǔn)包裝: 400
系列: 78K0S/Kx1+
核心處理器: 78K0S
芯體尺寸: 8-位
速度: 10MHz
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 7
程序存儲(chǔ)器容量: 2KB(2K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 10-LSSOP(0.225",5.72mm 寬)
包裝: 托盤
CHAPTER 4 PORT FUNCTIONS
User’s Manual U18172EJ3V0UD
65
Figure 4-9. Block Diagram of P34 (
μPD78F920x)
RD
P34/RESET
Option
byte
Reset
Internal
bus
RD:
Read signal
Caution
Because the P34 pin functions alternately as the RESET pin, if it is used as an input port pin, the
function to input an external reset signal to the RESET pin cannot be used. The function of the
port is selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE.
Also, since the option byte is referenced after the reset release, if low level is input to the RESET
pin before the referencing, then the reset state is not released. When it is used as an input port
pin, connect the pull-up resistor.
Figure 4-10. Block Diagram of P34 (
μPD78F950x)
RD
P34/RESET
Reset
WRPU
PU34
PU3
P-ch
Internal
bus
Option byte
VDD
RD:
Read signal
Caution
Because the P34 pin functions alternately as the RESET pin, if it is used as an input port pin, the
function to input an external reset signal to the RESET pin cannot be used. The function of the
port is selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE.
Also, since the option byte is referenced after the reset release, if low level is input to the RESET
pin before the referencing, then the reset state is not released. When it is used as an input port
pin, connect an on-chip pull-up resistor by using bit 4 (PU34) of pull-up resistor option register 3
(PU3).
<R>
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