μPD78F920x ONLY) User’s Manual U18172EJ3V0UD 126 <3> Do" />
參數(shù)資料
型號(hào): UPD78F9201MA-CAC-A
廠商: Renesas Electronics America
文件頁數(shù): 33/158頁
文件大?。?/td> 0K
描述: MCU 8BIT 2KB FLASH 128B RAM
標(biāo)準(zhǔn)包裝: 400
系列: 78K0S/Kx1+
核心處理器: 78K0S
芯體尺寸: 8-位
速度: 10MHz
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 7
程序存儲(chǔ)器容量: 2KB(2K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 10-LSSOP(0.225",5.72mm 寬)
包裝: 托盤
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (
μPD78F920x ONLY)
User’s Manual U18172EJ3V0UD
126
<3>
Do not set the 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) to 0000H.
(12) One-shot pulse output with external trigger
<1>
Do not input the external trigger again while the one-shot pulse is output.
To output the one-shot pulse again, wait until the current one-shot pulse output is completed.
<2>
Do not set the 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) to 0000H.
(13) Operation of OVF00 flag
<1>
The OVF00 flag is also set to 1 in the following case.
Either of the clear & start mode entered on a match between TM00 and CR000, clear & start at the valid
edge of the TI000 pin, or free-running mode is selected.
CR000 is set to FFFFH.
When TM00 is counted up from FFFFH to 0000H.
Figure 6-38. Operation Timing of OVF00 Flag
Count clock
CR000
TM00
OVF00
INTTM000
FFFFH
FFFEH
FFFFH
0000H
0001H
<2>
Even if the OVF00 flag is cleared before the next count clock is counted (before TM00 becomes 0001H)
after the occurrence of a TM00 overflow, the OVF00 flag is reset newly and clear is disabled.
(14) Conflicting operations
If the register read period and the input of the capture trigger conflict when CR000/CR010 is used as a capture
register, the capture trigger input takes precedence and the read data is undefined. Also, if the count stop of
the timer and the input of the capture trigger conflict, the captured data is undefined.
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