參數(shù)資料
型號： UPD78F9201MA-CAC-A
廠商： Renesas Electronics America
文件頁數(shù)： 63/158頁
文件大?。?/td> 0K
描述： MCU 8BIT 2KB FLASH 128B RAM
標準包裝： 400
系列： 78K0S/Kx1+
核心處理器： 78K0S
芯體尺寸： 8-位
速度： 10MHz
外圍設(shè)備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 7
程序存儲器容量： 2KB（2K x 8）
程序存儲器類型： 閃存
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 10-LSSOP（0.225"，5.72mm 寬）
包裝： 托盤
CHAPTER 8 WATCHDOG TIMER
User’s Manual U18172EJ3V0UD
153
8.4.2
Watchdog timer operation when “l(fā)ow-speed internal oscillator can be stopped by software” is
selected by option byte
The operation clock of the watchdog timer can be selected as either the low-speed internal oscillation clock or
system clock.
After reset is released, operation is started at the maximum cycle of the low-speed internal oscillation clock (bits 2,
1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).
The following shows the watchdog timer operation after reset release.
1.
The status after reset release is as follows.
Operation clock: Low-speed internal oscillation clock
Cycle: 218/fRL (546.13 ms: At operation with fRL = 480 kHz (MAX.))
Counting starts
2.
The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instruction
Notes 1, 2, 3.
Operation clock: Any of the following can be selected using bits 3 and 4 (WDCS3 and WDCS4).
Low-speed internal oscillation clock (fRL)
Syatem clock (fX)
Watchdog timer operation stopped
Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
3.
After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Notes 1.
As soon as WDTM is written, the counter of the watchdog timer is cleared.
2.
Set bits 7, 6, and 5 to 0, 1, 1, respectively. Do not set the other values.
3.
At the first write, If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and
×,
respectively, an internal reset signal is not generated even if the following processing is performed.
WDTM is written a second time.
A 1-bit memory manipulation instruction is executed to WDTE.
A value other than ACH is written to WDTE.
Caution
In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution.
After HALT/STOP mode is released, counting is started again using the operation clock of the
watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter
is not cleared to 0 but holds its value.
For the watchdog timer operation during STOP mode and HALT mode in each status, see 8.4.3 Watchdog timer
operation in STOP mode and 8.4.4 Watchdog timer operation in HALT mode.
A status transition diagram is shown below.
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