μPD78F920x ONLY) User’s Manual U18172EJ3V0UD 93 When CR000 i" />
參數(shù)資料
型號: UPD78F9201MA-CAC-A
廠商: Renesas Electronics America
文件頁數(shù): 154/158頁
文件大?。?/td> 0K
描述: MCU 8BIT 2KB FLASH 128B RAM
標(biāo)準(zhǔn)包裝: 400
系列: 78K0S/Kx1+
核心處理器: 78K0S
芯體尺寸: 8-位
速度: 10MHz
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 7
程序存儲器容量: 2KB(2K x 8)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 10-LSSOP(0.225",5.72mm 寬)
包裝: 托盤
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (
μPD78F920x ONLY)
User’s Manual U18172EJ3V0UD
93
When CR000 is used as a capture register
It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. Setting of the
TI000 or TI010 valid edge is performed by means of prescaler mode register 00 (PRM00) (refer to Table 6-
2).
Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins
(1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1)
CR000 Capture Trigger
TI000 Pin Valid Edge
ES010
ES000
Falling edge
Rising edge
0
1
Rising edge
Falling edge
0
No capture operation
Both rising and falling edges
1
(2) TI010 pin valid edge selected as capture trigger (CRC001 = 0, CRC000 = 1)
CR000 Capture Trigger
TI010 Pin Valid Edge
ES110
ES100
Falling edge
0
Rising edge
0
1
Both rising and falling edges
1
Remarks 1. Setting ES010, ES000 = 1, 0 and ES110, ES100 = 1, 0 is prohibited.
2. ES010, ES000:
Bits 5 and 4 of prescaler mode register 00 (PRM00)
ES110, ES100:
Bits 7 and 6 of prescaler mode register 00 (PRM00)
CRC001, CRC000: Bits 1 and 0 of capture/compare control register 00 (CRC00)
Cautions 1. Set CR000 to other than 0000H in the clear & start mode entered on match between TM00
and CR000.
This means a 1-pulse count operation cannot be performed when this
register is used as an external event counter. However, in the free-running mode and in
the clear & start mode using the valid edge of TI000, if CR000 is set to 0000H, an interrupt
request (INTTM000) is generated when CR000 changes from 0000H to 0001H following
overflow (FFFFH).
2. If the new value of CR000 is less than the value of 16-bit timer counter 0 (TM00), TM00
continues counting, overflows, and then starts counting from 0 again. If the new value of
CR000 is less than the old value, therefore, the timer must be reset to be restarted after
the value of CR000 is changed.
3. The value of CR000 after 16-bit timer/event counter 00 has stopped is not guaranteed.
4. The capture operation may not be performed for CR000 set in compare mode even if a
capture trigger is input.
5. When P21 is used as the input pin for the valid edge of TI010, it cannot be used as a timer
output (TO00). Moreover, when P21 is used as TO00, it cannot be used as the input pin
for the valid edge of TI010.
6. If the register read period and the input of the capture trigger conflict when CR000 is
used as a capture register, the read data is undefined (the capture data itself is a normal
value). Also, if the count stop of the timer and the input of the capture trigger conflict,
the capture trigger is undefined.
7. Changing the CR000 setting may cause a malfunction. To change the setting, refer to 6.5
Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare register
during timer operation.
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