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參數(shù)資料
| 型號： | UPD98404GJ-KEU |
| 廠商： | NEC Corp. |
| 英文描述： | E Core |
| 中文描述： | 高級自動柜員機的SONET成幀器 |
| 文件頁數(shù)： | 12/36頁 |
| 文件大?。?/td> | 201K |
| 代理商： | UPD98404GJ-KEU |
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Data Sheet S11822EJ4V0DS00
12
μ
PD98404
(2/2)
Pin name
Pin No.
I/O level
I/O
Function
EMPTY_B/
RCLAV
125
TTL*
O
(2 or 3-
state)
Receive FIFO data transfer disable signal output or
receive FIFO cell data transfer enable signal output.
This pin functions as either EMPTY_B (2-state operation) or RCLAV
(3-state operation), depending on the selected mode of the UTOPIA
interface.
EMPTY_B indicates that the receive FIFO has no receive data bytes
to be transferred to the ATM layer.
RCLAV indicates that the receive FIFO has data of at least once cell
to be transferred to the ATM layer. This pin operates in two or three
states, depending on the UTOPIA interface mode.
RADD0-
RADD4
138-142
TTL*
I
PHY address input for the receive side. In multi-PHY mode, these
pins input the address of the PHY layer device to be selected.
TDI0-
TDI7
111-118
TTL*
I
Transmit data input. These pins form an 8-bit data bus that inputs
transmit data. The data is input in sync with the rising edge of the
TCLK clock.
TCLK
120
TTL*
I
Transmit clock input. This pin inputs a clock of 20 to 40 MHz for
transmit data transfer.
Caution The
μ
PD98404 also uses this clock as the system clock
of the management interface block. Therefore, always
input a clock of 20 MHz or higher.
TSOC
122
TTL*
I
Transmit cell start position input.
This pin inputs a signal indicating the position of the first byte of the
transmit cell input to the
μ
PD98404.
TENBL_B
121
TTL*
I
Transmit enable input.
This pin inputs a signal indicating that an ATM layer device is
outputting valid transmit data to TDI0 - TDI7.
FULL_B/
TCLAV
123
TTL*
O
(2 or 3-
state)
Transmit FIFO data transfer disable signal output or transmit FIFO
cell data transfer enable signal output.
This pin functions as either FULL_B (2-state operation) or TCLAV (3-
state operation), depending on the selected UTOPIA interface mode.
FULL_B indicates that the transmit FIFO has no free area to receive
transmit data. TCLAV indicates that the transmit FIFO has a free
area of at least one cell for storing transmit data. This pin operates in
two or three states, depending on the UTOPIA interface mode.
TADD0-
TADD4
103-107
TTL*
I
PHY address input for the transmit side. When used in multi-PHY
mode, these pins input an address for selecting a PHY layer device.
UMPSEL
85
TTL*
I
Multi-PHY mode select signal input.
When the signal is high, multi-PHY mode is selected.
When the signal is low, single PHY mode is selected.
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