
Data Sheet S11822EJ4V0DS00
15
μ
PD98404
1.5 Internal test pins
Pin name
Pin No.
I/O level
I/O
Function
TEST0-
TEST2
7-9
TTL*
I
These pins are used to test the
μ
PD98404. In normal operation, all
these pins should be grounded.
TEST [2:0] =000
: Normal operation
TEST [2:0] =Other than 000 : Test mode
1.6 Power and ground
Pin name
Pin No.
I/O
Function
VDD
1, 27, 36, 60, 73, 95,
108, 119, 129
-
Power supply (+3.3 V
±
5%) and ground for the general logic block.
GND
16, 37, 71, 72, 86, 102,
109, 110, 124, 143, 144
-
VDD-TPE
39, 45, 49
-
GND-TPE
42, 46
-
Power supply (+3.3 V
±
5%) and ground for output PECL I/O. Any
noise in this power supply will affect the jitter characteristics. A
means of eliminating this noise, such as a filter, is needed.
VDD-RPE
53
-
GND-RPE
50, 56
-
Power supply (+3.3 V
±
5%) and ground for input PECL I/O. Any
noise in this power supply will affect the jitter characteristics. A
means of eliminating this noise, such as a filter, is needed.
VDD-SP
35
-
GND-SP
38
-
Power supply (+3.3 V
±
5%) and ground for the serial /parallel block.
Any noise in this power supply will affect the jitter characteristics. A
means of eliminating this noise, such as a filter, is needed.
VDD-CS
32, 33
-
GND-CS
29, 30, 34
-
Power supply (+3.3 V
±
5%) and ground for the clock synthesizer PLL
block. Any noise in this power supply will affect the jitter
characteristics. A means of eliminating this noise, such as a filter, is
needed.
VDD-CR
58
-
GND-CR
57
-
Power supply (+3.3 V
±
5%) and ground for the clock recovery PLL
block. Any noise in this power supply will affect the jitter
characteristics. A means of eliminating this noise, such as a filter, is
needed.