參數(shù)資料
型號： V53C1256162VBLT8EPC
廠商： Electronic Theatre Controls, Inc.
英文描述： 256Mbit MOBILE SDRAM 2.5 VOLT FBGA PACKAGE 16M X 16
中文描述： 片256Mbit移動SDRAM 2.5伏FBGA封裝16米x 16
文件頁數(shù)： 15/46頁
文件大?。?/td> 541K
代理商： V53C1256162VBLT8EPC
15
V55C2256164VB Rev. 1.0 April 2005
ProMOS TECHNOLOGIES
V55C2256164VB
Notes for AC Parameters:
1.
For proper power-up see the operation section of this data sheet.
2.
AC timing tests are referenced to the 0.9V crossover point for VCCQ=1.8V components. The transition time is mea-
sured between V
IH
and V
IL
. All AC measurements assume t
T
= 1ns with the AC output load circuit shown in
Figure 1.
4.
If clock rising time is longer than 1 ns, a time (t
T
/2 – 0.5) ns has to be added to this parameter.
5.
If t
T
is longer than 1 ns, a time (t
T
– 1) ns has to be added to this parameter.
6.
These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
Refresh Cycle
19
t
REF
Refresh Period (8192 cycles)
—
64
—
64
—
64
ms
20
t
SREX
Self Refresh Exit Time
1
—
1
—
1
—
CLK
Read Cycle
21
t
OH
Data Out Hold Time
3
–
3
–
3
–
ns
2
22
t
LZ
Data Out to Low Impedance Time
1
–
1
–
1
–
ns
23
t
HZ
Data Out to High Impedance Time
3
7
3
7
3
7
ns
7
24
t
DQZ
DQM Data Out Disable Latency
–
2
–
2
–
2
CLK
Write Cycle
25
t
WR
Write Recovery Time
1
–
1
–
1
–
CLK
26
t
DQW
DQM Write Mask Latency
0
–
0
–
0
–
CLK
#
Symbol Parameter
Limit Values
Unit
Note
-7
-8PC
-10
Min.
Max.
Min.
Max.
Min.
Max.
1.4V
1.4V
tCS
tCH
tAC
tAC
tLZ
tOH
tHZ
CLK
COMMAND
OUTPUT
50 pF
I/O
Z=50 Ohm
+ 1.4 V
50 Ohm
VIH
VIL
t
T
Figure 1.
tCK
AC Characteristics
(Cont’d)
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