參數(shù)資料
型號(hào)： V53C1256162VBLT8EPC
廠商： Electronic Theatre Controls, Inc.
英文描述： 256Mbit MOBILE SDRAM 2.5 VOLT FBGA PACKAGE 16M X 16
中文描述： 片256Mbit移動(dòng)SDRAM 2.5伏FBGA封裝16米x 16
文件頁(yè)數(shù)： 5/46頁(yè)
文件大小： 541K
代理商： V53C1256162VBLT8EPC
5
V55C2256164VB Rev. 1.0 April 2005
ProMOS TECHNOLOGIES
V55C2256164VB
Description
The V55C2256164VB is a four bank Synchronous DRAM organized as 4 banks x 4Mbit x 16. The
V55C2256164VB achieves high speed data transfer rates up to 143 MHz by employing a chip architecture
that prefetches multiple bits and then synchronizes the output data to a system clock.
All of the control, address, data input and output circuits are synchronized with the positive edge of an ex-
ternally supplied clock.
Operating the four memory banks in an interleaved fashion allows random access operation to occur at
higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 143 MHz is
possible depending on burst length, CAS latency and speed grade of the device.
Signal Pin Description
Pin
Type
Signal
Polarity
Function
CLK
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.
CKE
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode or the Self Refresh mode.
CS
Input
Pulse
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
RAS, CAS
WE
Input
Pulse
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
A0 - A12
Input
Level
—
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
8M x 16 SDRAM CA0–CA8.
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are
used to define which bank to precharge.
BA0,
BA1
Input
Level
—
Selects which bank is to be active.
DQx
Input
Output
Level
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
LDQM
UDQM
Input
Pulse
Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high.
VCC, VSS
Supply
Power and ground for the input buffers and the core logic.
VCCQ
VSSQ
Supply
—
—
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
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V53C1256162VBLT8PC 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:256Mbit MOBILE SDRAM 2.5 VOLT FBGA PACKAGE 16M X 16
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