參數(shù)資料
型號： VDP3104B
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
元件分類： 消費家電
英文描述： Video Processor Family
中文描述： SPECIALTY CONSUMER CIRCUIT, PDIP64
封裝： SHRINK, PLASTIC, DIP-64
文件頁數(shù)： 19/72頁
文件大?。?/td> 603K
代理商： VDP3104B
PRELIMINARY DATA SHEET
VDP 31xxB
19
Micronas
2.8.12. Picture Frame Generator
When the picture does not fill the total screen (height or
width too small) it is surrounded with black areas. These
areas (and more) can be colored with the picture frame
generator. This is done by switching over the RGB signal
from the matrix to the signal from the OSD color look-up
table.
The width of each area (left, right, upper, lower) can be
adjusted separately. The generator starts on the right,
respectively lower side of the screen and stops on the
left, respectively upper side of the screen. This means,
it runs during horizontal, respectively vertical flyback.
The color of the complete border can be stored in the
programmable OSD color look-up table in a separate
address. The format is 3
4 bit RGB. The contrast can
be adjusted separately.
The picture frame generator includes a priority master
circuit. Its priority is programmable and the border is
generated only if the priority is higher than the priority at
the PRIO bus. Therefore the border can be underlay or
overlay depending on the picture source.
2.8.13. Priority Codec
The priority decoder has three input lines for up to eight
priorities. The highest priority is all three lines at low lev-
el. A 5-bit information is attached to each priority (see
table 3
–
1
‘
Priority Bus
’
). These bits are programmable
via the I
2
C-bus and have the following meanings:
–
one of two contrast, brightness and matrix values for
main and side picture
–
RGB from video signal or color look-up table
–
disable/enable black level expander
–
disable/enable peaking transient suppression when
signal is switched
–
disable/enable analog fast blank input 1
–
disable/enable analog fast blank input 2
2.8.14. Scan Velocity Modulation
The RGB input signal of the SVM is converted to Y in a
simple matrix. Then the Y signal is differentiated by a fil-
ter of the transfer function 1
–
Z
–
N
, where N is program-
mable from 1 to 6. With a coring, some noise can be sup-
pressed. This is followed by a gain adjustment and an
adjustable limiter. The analog output signal is generated
by an 8-bit D/A converter.
The signal delay can be adjusted by
±
3.5 clocks in half-
clock steps. For the gain and filter adjustment there are
two parameter sets. The switching between these two
sets is done with the same RGB switch signal that is
used for switching between video-RGB and OSD-RGB
for the RGB outputs. (See Fig. 2
–
19).
2.8.15. Display Phase Shifter
A phase shifter is used to partially compensate the
phase differences between the video source and the fly-
back signal. By using the described clock system, this
phase shifter works with an accuracy of approximately
1 ns. It has a range of 1 clock period which is equivalent
to
±
24.7 ns at 20.25 MHz. The large amount of phase
shift (full clock periods) is realized in the front-end circuit.
Fig. 2
–
19:
SVM block diagram
G
R
B
Matrix and
Shaping
Modulation
Notch
Differen-
tiator
1
–
Z
–
Nx
N1
N2
Coring
adjustment
Gain
adjustment
Limiter
Delay
adjustment
D/A
Converter
Coring
Gain1
Gain2
Limit
Delay
RGB Switch
Output
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