參數(shù)資料
型號(hào)： VDP3104B
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
元件分類： 消費(fèi)家電
英文描述： Video Processor Family
中文描述： SPECIALTY CONSUMER CIRCUIT, PDIP64
封裝： SHRINK, PLASTIC, DIP-64
文件頁數(shù)： 7/72頁
文件大?。?/td> 603K
代理商： VDP3104B
PRELIMINARY DATA SHEET
VDP 31xxB
7
Micronas
2. Functional Description
2.1. Analog Front-End
This block provides the analog interfaces to all video in-
puts and mainly carries out analog-to digital conversion
for the following digital video processing. A block dia-
gram is given in Fig. 2
–
1.
Most of the functional blocks in the front-end are digitally
controlled (clamping, AGC, and clock-DCO). The con-
trol loops are closed by the Fast Processor (
‘
FP
’
) em-
bedded in the decoder.
2.1.1. Input Selector
Up to five analog inputs can be connected. Four inputs
are for input of composite video or S-VHS luma signal.
These inputs are clamped to the sync back porch and
are amplified by a variable gain amplifier. One input is
for connection of S-VHS carrier-chrominance signal.
This input is internally biased and has a fixed gain ampli-
fier.
2.1.2. Clamping
The composite video input signals are AC coupled to the
IC. The clamping voltage is stored on the coupling ca-
pacitors and is generated by digitally controlled current
sources. The clamping level is the back porch of the vid-
eo signal. S-VHS chroma is also AC coupled. The input
pin is internally biased to the center of the ADC input
range.
2.1.3. Automatic Gain Control
A digitally working automatic gain control adjusts the
magnitude of the selected baseband by +6/
–
4.5 dB in 64
logarithmic steps to the optimal range of the ADC. The
gain of the video input stage including the ADC is 213
steps/V with the AGC set to 0 dB.
2.1.4. Analog-to-Digital Converters
Two ADCs are provided to digitize the input signals.
Each converter runs with 20.25 MHz and has 8 bit reso-
lution. An integrated bandgap circuit generates the re-
quired reference voltages for the converters.
2.1.5. ADC Range
The ADC input range for the various input signals and
the digital representation is given in Table 2
–
1 and Fig.
2
–
2. The corresponding output signal levels of the
VDP 31xxB are also shown.
2.1.6. Digitally Controlled Clock Oscillator
The clock generation is also a part of the analog front
end. The crystal oscillator is controlled digitally by the
control processor; the clock frequency can be adjusted
within
±
150 ppm.
2.1.7. Analog Video Output
The input signal of the Luma ADC is available at the ana-
log video output pin. The signal at this pin must be buff-
ered by a source follower. The output voltage is 2 V, thus
the signal can be used to drive a 75 line. The magni-
tude is adjusted with an AGC in 8 steps together with the
main AGC.
DVCO
±
150
ppm
i
m
clamp
bias
frequency
20.25 MHz
gain
ADC
AGC
+6/
–
4.5 dB
reference
generation
ADC
VIN3
Fig. 2
–
1:
Analog front-end
VIN2
VIN1
CIN
digital Chroma
digital CVBS or Luma
system clocks
CVBS/Y
CVBS/Y
CVBS/Y/C
Chroma
Analog Video
Output
3
VIN4
CVBS/Y
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