參數(shù)資料
型號(hào)： VDP3104B
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
元件分類： 消費(fèi)家電
英文描述： Video Processor Family
中文描述： SPECIALTY CONSUMER CIRCUIT, PDIP64
封裝： SHRINK, PLASTIC, DIP-64
文件頁數(shù)： 39/72頁
文件大小： 603K
代理商： VDP3104B
PRELIMINARY DATA SHEET
VDP 31xxB
39
Micronas
Table 3
–
3:
Control Registers of the Fast Processor for control of front-end functions
–
default values are initialized at reset
FP Sub-
address
Function
Default
Name
Standard Selection
h
’
20
Standard select:
bit[2:0]
standard
0
1
2
3
4
5
6
7
0/1
PAL B,G,H,I (50 Hz)
NTSC M
SECAM
NTSC44
PAL M
PAL N
PAL 60
NTSC COMB(60 Hz)
standard modifier
PAL modified to simple PAL
NTSC modified to compensated NTSC
SECAM modified to monochrome 625
NTSCC modified to monochrome 525
reserved (set to 0)
0/1
2-H comb filter off/on
0/1
S-VHS mode off/on
4.433618
3.579545
4.286
4.433618
3.575611
3.582056
4.433618
3.579545
(60 Hz)
(50 Hz)
(60 Hz)
(60 Hz)
(50 Hz)
(60 Hz)
bit[3]
bit[4]
bit[5]
bit[6]
Option bits allow to suppress parts of the initialization, this can be used
for color standard search:
bit[7]
bit[8]
bit[9]
bit[10]
no hpll setup
no vertical setup
no acc setup
2-H comb filter set-up only
bit[11]
status bit, normally write 0. After the FP has switched to a
new standard, this bit is set to 1 to indicate operation
complete. Standard is automatically initialized when the
insel register is written.
0
sdt
pal
ntsc
secam
ntsc44
palm
paln
pal60
ntscc
sdtmod
comb
svhs
sdtopt
h
’
22
picture start position, this register sets the start point of active video, this
can be used e.g. for panning. The setting is updated when
’
sdt
’
register
is updated.
0
sfif
h
’
23
luma/chroma delay adjust. The setting is updated when
’
sdt
’
register is
updated.
bit[5:0]
reserved, set to zero
bit[11:6]
luma delay in clocks, allowed range is +1 ...
–
7
0
ldly
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