VDP 3108
ADVANCE INFORMATION
MICRONAS INTERMETALL
38
Short Description
Type
Pin Name
Connection
(if not used)
Pin No.
SDIL
64-pin
PLCC
68-pin
64
37
GND
F
ISGND
Signal Ground for Analog Input
65
36
H
OUT
HFLB
Horizontal Flyback Input
66
35
GND
O
SAFETY
Safety Input
67
34
GND
O
VPROT
Vertical Protection Input
68
33
LV
FSY
Front Sync
4.3. Pin Descriptions (pin numbers for 68–PLCC)
Pin 1 – Main Sync Pulse MSY (Fig. 4–8)
This pin supplies the main sync information.
Pin 2 – Reset Input RES (Fig. 4–5)
A low level on this pin resets the VDP3108.
Pin 3 – Test Input TEST (Fig. 4–5)
This pin enables factory test modes. For normal opera-
tion it must be connected to ground.
Pin 4 – Composite Sync Output CSY (Fig. 4–6)
This output supplies a standard composite sync signal
that is compatible to the analog RGB output signals.
Pin 5–7, 11–15 Picture Bus Luma L7 – L0 (Fig. 4–8)
The Picture Bus Luma lines carry the digital luminance
data. The data are sampled at 20.25 MHz.
In 5-bit RGB mode the 3 LSB L0,L1,L2 are the 1-bit
R,G,B color signals.
Pin 8 – Standby Supply Voltage V
STDBY
In standby mode, only the clock oscillator and the hori-
zontal drive circuitry are active.
Pin 9 – Horizontal Drive HOUT (Fig. 4–9)
This open drain output supplies the the drive pulse for
the horizontal output stage. The polarity and gating with
the flyback pulse are selectable by software.
Pin 10 – CCU 5 MHz Clock Output Clk5 (Fig. 4–6)
This pin provides a clock frequency for the TV microcon-
troller, e.g. a CCU3000 controller.
Pin 16 – Ground, Digital Circuitry GND
D
Pin 17,18 – XTAL1 Crystal Input and XTAL2 Crystal
Output (Fig. 4–10)
These pins are connected to an 20.25 MHz crystal oscil-
lator is digitally tuned by integrated shunt capacitances.
The Clk20 and Clk5 clock signals are derived from this
oscillator. An external clock can be fed into XTAL1. In
this case clock frequency adjustment must be switched
off.
Pin 19 – Supply Voltage, Digital Circuitry V
SUPD
Pin 20 – I
2
C Data SDA (Fig. 4–18)
This pin connects to the I
2
C bus data line.
Pin 21–25, 27–29 – Picture Bus Chroma
C0–C7 (Fig. 4–8)
The Picture Bus Chroma lines carry the digital UV chro-
minance data. The data are sampled at 10.125 MHz and
multiplexed. The UV multiplex is reset for each TV line.
In 5-bit RGB mode the two LSB UV0,UV1 are the C0,C1
bits of the 5-bit RGB signal. If C1 is 0 the RGB signals
are displayed in half contrast mode; if C1 is 1 the 4 bits
C0, R, G, B address one of the 16 entries of the color
map.
Pin 26 – I
2
C Clock SCL (Fig. 4–18)
This pin connects to the I
2
C bus clock line.
Pin 30–32 – Picture Bus Priority PR0–PR2 (Fig. 4–8)
The Picture Bus Priority lines carry the digital priority
selection signals. The priority interface allows digital
switching of up to 8 sources to the backend processor.
Switching for different sources is prioritized and can be
on a per pixel basis.
Pin 33 – Vertical Sawtooth Output VERT (Fig. 4–11 )
This pin supplies the drive signal for the vertical output
stage. The drive signal is generated with 15-bit precision
by the internal Fast Processor. The analog voltage is
generated with a 4 bit R-DAC and uses digital noise
shaping.
Pin 34,36,38 – Analog RGB Input RIN, GIN, BIN
(Fig. 4–12)
These pins are used to insert an external analog RGB
signal, e.g. from a SCART connector, to the analog RGB
outputs. The analog backend provides separate bright-
ness and contrast settings for the external analog RGB
signals.
Pin 35 – East–West Parabola Output EW (Fig. 4–11)
This pin supplies the parabola signal for the East-West
correction. The drive signal is generated with 15 bit pre-
cision by the internal Fast Processor. The analog volt-