參數(shù)資料
型號(hào)： VDP3108
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
英文描述： Single-Chip Video Processor
中文描述： 單芯片視頻處理器
文件頁數(shù)： 4/61頁
文件大?。?/td> 2638K
代理商： VDP3108
VDP 3108
ADVANCE INFORMATION
MICRONAS INTERMETALL
4
Single-Chip Video Processor
1. Introduction
The entire video processing and controlling for a color
TV has been developed on a single chip in 0.8
μ
CMOS
technology. Modular design and submicron technology
allow the economic integration of features in all classes
of TV sets.
Open architecture is the key word to the new DSP gener-
ation. Flexible standard building blocks have been de-
fined that offer continuity and transparency of the entire
system.
One IC contains the entire video and deflection process-
ing and builds the heart of a modern color TV. Its per-
formance and complexity allow the user to standardize
his product development. Hardware and software appli-
cations can profit from the modularity as well as man-
ufacturing, system support or maintenance. The main
features are:
– low cost, high performance
– all digital video processing
– multi-standard color decoder PAL/NTSC/SECAM
– 3 composite, 1 S–VHS input
– integrated high-quality AD/DA converters
– sync and deflection processing
– luminance and chrominance features, e.g.
peaking, color transient improvement
– programmable RGB matrix
– various digital interfaces
– embedded RISC controller (80 MIPS)
– one crystal, few external components
– single power supply 5 V
– 0.8
μ
CMOS Technology
– 68-pin PLCC or 64-pin Shrink DIL Package
1.1. System Architecture
Two main modules have been defined:
Video Processor and
Display Processor.
They are designed as silicon building blocks. Their parti-
tioning permits a variety of IC configurations with the aim
to satisfy the particular requirements of different appli-
cations. Both, analog and digital interfaces, support
state of the art TV receivers as well as other environ-
ments. Fig. 1–1 shows the block diagram of the single-
chip Video Processor which consists of both modules.
feature
interface
V2/Y
C
G
B
20.25
MHz
Hor.
Flyback
H/V
Drive
Analog
RGB
Color Decoder
Display Processor
Sync and Deflection
Clock Gen.
NTSC/PAL/SECAM
2*ADC,
8 bit
V1
V3
YC
r
C
b
–> RGB
Frontend
Backend
3*DAC,
10 bit
3 PLLs, horizontal output, vertical outputs
DCO
I
2
C
R
Fig. 1–1:
VDP block diagram
Fast
Blank
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