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參數(shù)資料
| 型號： | VDP3108 |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Single-Chip Video Processor |
| 中文描述： | 單芯片視頻處理器 |
| 文件頁數(shù)： | 5/61頁 |
| 文件大小： | 2638K |
| 代理商： | VDP3108 |
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ADVANCE INFORMATION
VDP 3108
MICRONAS INTERMETALL
5
2. Functional Description
2.1. Analog Front End
This block provides the analog interfaces to all video in-
puts and mainly carries out analog-to digital conversion
for the following digital video processing. A block dia-
gram is given in figure 2–1.
Most of the functional blocks in the front end are digitally
controlled (clamping, AGC and clock-DCO). The control
loops are closed by the Fast Processor (‘FP’) embedded
in the decoder.
2.1.1. Input Selector
Up to four analog inputs can be connected. Three inputs
are for input of composite video or S–VHS luma signal.
These inputs are clamped to the sync back porch and
are amplified by a variable gain amplifier. One input is
for connection of S–VHS carrier–chrominance signal.
This input is internally biased and has a fixed gain ampli-
fier.
2.1.2. Clamping
The composite video input signals are AC coupled to the
IC. The clamping voltage is stored on the coupling ca-
pacitors and is generated by digitally controlled current
sources. The clamping level is the back porch of the vid-
eo signal. S-VHS chroma is also AC coupled. The input
pin is internally biased to the center of the ADC input
range.
2.1.3. Automatic Gain Control
A digitally working automatic gain control adjusts the
magnitude of the selected baseband by +6/–4.5 dB in 64
logarithmic steps to the optimal range of the ADC .
The gain of the video input stage including the ADC is
213 steps/V for all three standards (PAL/NTSC/SECAM/
Y/C), with the AGC set to 0 dB.
2.1.4. Analog-to-Digital Converters
Two ADCs are provided to digitize the input signals.
Each converter runs with 20.25 MHz and has 8 bit reso-
lution. An integrated bandgap circuit generates the re-
quired reference voltages for the converters.
The two ADCs are of a 2-stage subranging type.
2.1.5. ADC Range
The ADC input range for the various input signals and
the digital representation is given in table 2–1 and figure
2–2.
2.1.6. Digitally Controlled Clock Oscillator
The clock generation is also a part of the analog front
end. The crystal oscillator is controlled digitally by the
control processor; the clock frequency can be adjusted
within
±
150 ppm.
o
m
i
m
clamp
level
bias/
clamp
DAC
freq.
frequ.
doubler
frequ.
divider
20.25
MHz
DAC
gain
ADC
AGC
+6/–4.5dB
reference
generation
ADC
8
8
VIN3
level
select
Fig. 2–1:
Analog front end
VIN2
VIN1
CIN
to
color
decod-
er
digital
chro-
ma
digital
CVBS
or Y
sys-
tem
clocks
DVC
O
±
150
ppm
CVBS/Y
CVBS/Y
CVBS/
Y/C
C
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| VDP3108B | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Processor Family |
| VDP3108PR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Consumer IC |
| VDP3112B | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Processor Family |
| VDP3116B | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Processor Family |
| VDP3120B | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Processor Family |
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